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authorAli Saidi <saidi@eecs.umich.edu>2010-07-27 01:03:44 -0400
committerAli Saidi <saidi@eecs.umich.edu>2010-07-27 01:03:44 -0400
commit1b73376b0bb04f25b4a7ef80bcd6ad0739f5b926 (patch)
tree8deb8fa950c8c4045cb9492804ebfb6b5731499f /tests/long/10.mcf/ref/arm/linux
parent97d245278d4b4bee844c141c3b6f370e27f73a45 (diff)
downloadgem5-1b73376b0bb04f25b4a7ef80bcd6ad0739f5b926.tar.xz
ARM: Add regression tests
Diffstat (limited to 'tests/long/10.mcf/ref/arm/linux')
-rw-r--r--tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini90
-rwxr-xr-xtests/long/10.mcf/ref/arm/linux/simple-atomic/simerr3
-rwxr-xr-xtests/long/10.mcf/ref/arm/linux/simple-atomic/simout31
-rw-r--r--tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt36
-rw-r--r--tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini190
-rwxr-xr-xtests/long/10.mcf/ref/arm/linux/simple-timing/simerr3
-rwxr-xr-xtests/long/10.mcf/ref/arm/linux/simple-timing/simout31
-rw-r--r--tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt233
8 files changed, 617 insertions, 0 deletions
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..51e730713
--- /dev/null
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -0,0 +1,90 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr
new file mode 100755
index 000000000..eabe42249
--- /dev/null
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr
@@ -0,0 +1,3 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
new file mode 100755
index 000000000..c7a7ab51b
--- /dev/null
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
@@ -0,0 +1,31 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 25 2010 20:52:35
+M5 revision ffac9df60637 7512 default tip
+M5 started Jul 26 2010 23:59:27
+M5 executing on zizzer
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+MCF SPEC version 1.6.I
+by Andreas Loebel
+Copyright (c) 1998,1999 ZIB Berlin
+All Rights Reserved.
+
+nodes : 500
+active arcs : 1905
+simplex iterations : 1502
+flow value : 4990014995
+new implicit arcs : 23867
+active arcs : 25772
+simplex iterations : 2663
+flow value : 3080014995
+checksum : 68389
+optimal
+Exiting @ tick 54182628000 because target called exit()
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..80fc2bb27
--- /dev/null
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -0,0 +1,36 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 2639601 # Simulator instruction rate (inst/s)
+host_mem_usage 330716 # Number of bytes of host memory used
+host_seconds 34.53 # Real time elapsed on the host
+host_tick_rate 1569281777 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 91136893 # Number of instructions simulated
+sim_seconds 0.054183 # Number of seconds simulated
+sim_ticks 54182628000 # Number of ticks simulated
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 108365257 # number of cpu cycles simulated
+system.cpu.num_insts 91136893 # Number of instructions executed
+system.cpu.num_refs 27330336 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
new file mode 100644
index 000000000..7b31977b8
--- /dev/null
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -0,0 +1,190 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr
new file mode 100755
index 000000000..eabe42249
--- /dev/null
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr
@@ -0,0 +1,3 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
new file mode 100755
index 000000000..d65963e33
--- /dev/null
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
@@ -0,0 +1,31 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 25 2010 20:52:35
+M5 revision ffac9df60637 7512 default tip
+M5 started Jul 26 2010 23:53:12
+M5 executing on zizzer
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+MCF SPEC version 1.6.I
+by Andreas Loebel
+Copyright (c) 1998,1999 ZIB Berlin
+All Rights Reserved.
+
+nodes : 500
+active arcs : 1905
+simplex iterations : 1502
+flow value : 4990014995
+new implicit arcs : 23867
+active arcs : 25772
+simplex iterations : 2663
+flow value : 3080014995
+checksum : 68389
+optimal
+Exiting @ tick 152158072000 because target called exit()
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..ae84c8f2c
--- /dev/null
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -0,0 +1,233 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1187634 # Simulator instruction rate (inst/s)
+host_mem_usage 338364 # Number of bytes of host memory used
+host_seconds 76.72 # Real time elapsed on the host
+host_tick_rate 1983393949 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 91110245 # Number of instructions simulated
+sim_seconds 0.152158 # Number of seconds simulated
+sim_ticks 152158072000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 22564820 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 14013.903608 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.903608 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 21664622 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 12615288000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.039894 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 900198 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 9914694000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.039894 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 900198 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 4738868 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 4642722 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 5384176000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.020289 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 96146 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 5095738000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.020289 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 96146 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 27.837649 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 27303688 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 18065.511510 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 15065.511510 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 26307344 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 17999464000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.036491 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 996344 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 15010432000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.036491 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 996344 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.874740 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 3582.934837 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 27303688 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 18065.511510 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 15065.511510 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 26307344 # number of overall hits
+system.cpu.dcache.overall_miss_latency 17999464000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.036491 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 996344 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 15010432000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.036491 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 996344 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements 942711 # number of replacements
+system.cpu.dcache.sampled_refs 946807 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 3582.934837 # Cycle average of tags in use
+system.cpu.dcache.total_refs 26356881 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 54489025000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 96053 # number of writebacks
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.icache.ReadReq_accesses 107819118 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 54667.779633 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 51667.779633 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 107818519 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 32746000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 599 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 30949000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 599 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 179997.527546 # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 107819118 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 54667.779633 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 51667.779633 # average overall mshr miss latency
+system.cpu.icache.demand_hits 107818519 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 32746000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses
+system.cpu.icache.demand_misses 599 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 30949000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 599 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.249734 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 511.454894 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 107819118 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 54667.779633 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 51667.779633 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 107818519 # number of overall hits
+system.cpu.icache.overall_miss_latency 32746000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses
+system.cpu.icache.overall_misses 599 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 30949000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 599 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.replacements 2 # number of replacements
+system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 511.454894 # Cycle average of tags in use
+system.cpu.icache.total_refs 107818519 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses 46609 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 2423668000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 46609 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1864360000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 46609 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 900797 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 899919 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 45656000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.000975 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 878 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 35120000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.000975 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 878 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 49537 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 2575924000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 49537 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1981480000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 49537 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 96053 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 96053 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 52.567404 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 947406 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 899919 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 2469324000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.050123 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 47487 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 1899480000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.050123 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 47487 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.009182 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.265752 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 300.880505 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 8708.164911 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 947406 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 899919 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 2469324000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.050123 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 47487 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 1899480000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.050123 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 47487 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.replacements 678 # number of replacements
+system.cpu.l2cache.sampled_refs 15333 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 9009.045417 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 806016 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 35 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 304316144 # number of cpu cycles simulated
+system.cpu.num_insts 91110245 # Number of instructions executed
+system.cpu.num_refs 27330336 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
+
+---------- End Simulation Statistics ----------