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authorGabe Black <gblack@eecs.umich.edu>2011-02-07 19:23:13 -0800
committerGabe Black <gblack@eecs.umich.edu>2011-02-07 19:23:13 -0800
commit0851580aada37c8e1b1d2b695100fbcfaf4e0946 (patch)
tree96eea53d6309ddb9f4bfac61767e53bfcdb44037 /tests/long/10.mcf/ref/arm/linux
parent1b64bfa933745294667158d0ce22180780b2a22e (diff)
downloadgem5-0851580aada37c8e1b1d2b695100fbcfaf4e0946.tar.xz
Stats: Re update stats.
Diffstat (limited to 'tests/long/10.mcf/ref/arm/linux')
-rw-r--r--tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini15
-rwxr-xr-xtests/long/10.mcf/ref/arm/linux/o3-timing/simout8
-rw-r--r--tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt31
-rw-r--r--tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini17
-rwxr-xr-xtests/long/10.mcf/ref/arm/linux/simple-atomic/simout10
-rw-r--r--tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt26
-rw-r--r--tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini17
-rwxr-xr-xtests/long/10.mcf/ref/arm/linux/simple-timing/simerr4
-rwxr-xr-xtests/long/10.mcf/ref/arm/linux/simple-timing/simout10
-rw-r--r--tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt26
10 files changed, 125 insertions, 39 deletions
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
index 67f0de766..9285fee06 100644
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=DerivO3CPU
@@ -484,9 +493,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
index 43dc1d1fc..591032c8f 100755
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jan 11 2011 18:16:01
-M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
-M5 started Jan 12 2011 03:03:04
-M5 executing on u200439-lin.austin.arm.com
+M5 compiled Feb 7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb 7 2011 01:58:27
+M5 executing on burrito
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 674012633..390072636 100644
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 109166 # Simulator instruction rate (inst/s)
-host_mem_usage 384348 # Number of bytes of host memory used
-host_seconds 835.45 # Real time elapsed on the host
-host_tick_rate 67095197 # Simulator tick rate (ticks/s)
+host_inst_rate 65288 # Simulator instruction rate (inst/s)
+host_mem_usage 370872 # Number of bytes of host memory used
+host_seconds 1396.92 # Real time elapsed on the host
+host_tick_rate 40127232 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91202735 # Number of instructions simulated
sim_seconds 0.056055 # Number of seconds simulated
@@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 109380669 # Number of insts commited each cycle
system.cpu.commit.COM:count 91202735 # Number of instructions committed
+system.cpu.commit.COM:fp_insts 48 # Number of committed floating point instructions.
+system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
+system.cpu.commit.COM:int_insts 72483223 # Number of committed integer instructions.
system.cpu.commit.COM:loads 22585492 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 27330336 # Number of memory references committed
@@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 112077802 # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads 75 # number of floating regfile reads
+system.cpu.fp_regfile_writes 47 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 12683523 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 36326.451613 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34504.457652 # average ReadReq mshr miss latency
@@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 788441 #
system.cpu.iew.memOrderViolationEvents 1330 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 76117 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 1979748 # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads 246289928 # number of integer regfile reads
+system.cpu.int_regfile_writes 76222702 # number of integer regfile writes
system.cpu.ipc 0.813516 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.813516 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
@@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 112077802 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.888775 # Inst issue rate
+system.cpu.iq.fp_alu_accesses 74 # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads 144 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses 100131195 # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads 311849254 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses 96607706 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes 112840034 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 102487226 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 99639939 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 553822 # Number of non-speculative instructions added to the IQ
@@ -463,7 +478,11 @@ system.cpu.memDep0.conflictingLoads 436025 # Nu
system.cpu.memDep0.conflictingStores 249497 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 24681131 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 5533285 # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads 157552604 # number of misc regfile reads
+system.cpu.misc_regfile_writes 1603309 # number of misc regfile writes
system.cpu.numCycles 112109302 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 294826 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 72061910 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 4906 # Number of times rename has blocked due to IQ full
@@ -476,10 +495,14 @@ system.cpu.rename.RENAME:RunCycles 72730212 # Nu
system.cpu.rename.RENAME:SquashCycles 2697133 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 723330 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 11862848 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups 474 # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups 277458644 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 5701177 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 592742 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 1065555 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 576556 # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads 212048427 # The number of ROB reads
+system.cpu.rob.rob_writes 208775903 # The number of ROB writes
system.cpu.timesIdled 1292 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
index bfff6943f..a584d29ed 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=AtomicSimpleCPU
@@ -52,14 +61,14 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
index d622d0388..34dd3ff53 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 18:40:32
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
+M5 compiled Feb 7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb 7 2011 01:56:24
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index 9bb34897d..0d4b35c47 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2560594 # Simulator instruction rate (inst/s)
-host_mem_usage 386656 # Number of bytes of host memory used
-host_seconds 35.62 # Real time elapsed on the host
-host_tick_rate 1522136495 # Simulator tick rate (ticks/s)
+host_inst_rate 937948 # Simulator instruction rate (inst/s)
+host_mem_usage 362060 # Number of bytes of host memory used
+host_seconds 97.24 # Real time elapsed on the host
+host_tick_rate 557562760 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91202735 # Number of instructions simulated
sim_seconds 0.054216 # Number of seconds simulated
@@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 108431099 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 108431099 # Number of busy cycles
+system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
+system.cpu.num_fp_insts 48 # number of float instructions
+system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 91202735 # Number of instructions executed
-system.cpu.num_refs 27330336 # Number of memory references
+system.cpu.num_int_alu_accesses 72483223 # Number of integer alu accesses
+system.cpu.num_int_insts 72483223 # number of integer instructions
+system.cpu.num_int_register_reads 234567931 # number of times the integer registers were read
+system.cpu.num_int_register_writes 72546720 # number of times the integer registers were written
+system.cpu.num_load_insts 22585492 # Number of load instructions
+system.cpu.num_mem_refs 27330336 # number of memory refs
+system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
index d78abde62..d7d6a4868 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -1,13 +1,22 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@@ -152,14 +161,14 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr
index eabe42249..c1c8fcec5 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,7 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
index c45082899..b290f1d74 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Oct 11 2010 18:37:23
-M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
-M5 started Oct 11 2010 18:41:18
-M5 executing on aus-bc3-b4
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
+M5 compiled Feb 7 2011 01:56:16
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb 7 2011 01:56:25
+M5 executing on burrito
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
index bb2ffd900..5c965f81e 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 587679 # Simulator instruction rate (inst/s)
-host_mem_usage 394372 # Number of bytes of host memory used
-host_seconds 155.15 # Real time elapsed on the host
-host_tick_rate 954493550 # Simulator tick rate (ticks/s)
+host_inst_rate 419592 # Simulator instruction rate (inst/s)
+host_mem_usage 369772 # Number of bytes of host memory used
+host_seconds 217.30 # Real time elapsed on the host
+host_tick_rate 681491064 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91176087 # Number of instructions simulated
sim_seconds 0.148086 # Number of seconds simulated
@@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 32 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 296172438 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 296172438 # Number of busy cycles
+system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
+system.cpu.num_fp_insts 48 # number of float instructions
+system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 91176087 # Number of instructions executed
-system.cpu.num_refs 27330336 # Number of memory references
+system.cpu.num_int_alu_accesses 72483223 # Number of integer alu accesses
+system.cpu.num_int_insts 72483223 # number of integer instructions
+system.cpu.num_int_register_reads 257112085 # number of times the integer registers were read
+system.cpu.num_int_register_writes 72558730 # number of times the integer registers were written
+system.cpu.num_load_insts 22585492 # Number of load instructions
+system.cpu.num_mem_refs 27330336 # number of memory refs
+system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
---------- End Simulation Statistics ----------