diff options
| author | Steve Reinhardt <stever@gmail.com> | 2010-09-09 14:40:19 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2010-09-09 14:40:19 -0400 |
| commit | 9e45ada1718b6df9310757fdc7cd78db4695516f (patch) | |
| tree | c5cc9f2173f36e38addd8ca08e32ac010e56ef73 /tests/long/10.mcf/ref/arm | |
| parent | 12497284949cb5418e6bc403723c034aee655666 (diff) | |
| download | gem5-9e45ada1718b6df9310757fdc7cd78db4695516f.tar.xz | |
stats: update stats for preceding coherence changes
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
Diffstat (limited to 'tests/long/10.mcf/ref/arm')
3 files changed, 86 insertions, 83 deletions
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini index c9498a09b..5e9ca96c9 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -152,7 +152,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing +cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout index 96976b990..de9fd3dbd 100755 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing/simout +Redirecting stderr to build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 24 2010 15:34:40 -M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase -M5 started Aug 24 2010 15:38:31 +M5 compiled Aug 26 2010 13:52:30 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 14:11:34 M5 executing on zizzer -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +30,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 152158072000 because target called exit() +Exiting @ tick 152155526000 because target called exit() diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt index 4acab86d6..82be14609 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1413696 # Simulator instruction rate (inst/s) -host_mem_usage 343480 # Number of bytes of host memory used -host_seconds 64.50 # Real time elapsed on the host -host_tick_rate 2359219725 # Simulator tick rate (ticks/s) +host_inst_rate 1008175 # Simulator instruction rate (inst/s) +host_mem_usage 344580 # Number of bytes of host memory used +host_seconds 90.44 # Real time elapsed on the host +host_tick_rate 1682447495 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91176087 # Number of instructions simulated -sim_seconds 0.152158 # Number of seconds simulated -sim_ticks 152158072000 # Number of ticks simulated +sim_seconds 0.152156 # Number of seconds simulated +sim_ticks 152155526000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 22564820 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 14013.903608 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.903608 # average ReadReq mshr miss latency @@ -19,15 +19,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 9914694000 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.039894 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 900198 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 4738868 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 4642722 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5384176000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.020289 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 96146 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 5095738000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.020289 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 96146 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 55998.688893 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52998.688893 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 4642766 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5381586000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.020280 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 96102 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5093280000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.020280 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 96102 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 27.837649 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 27303688 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18065.511510 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 15065.511510 # average overall mshr miss latency -system.cpu.dcache.demand_hits 26307344 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 17999464000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.036491 # miss rate for demand accesses -system.cpu.dcache.demand_misses 996344 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 18063.709726 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 15063.709726 # average overall mshr miss latency +system.cpu.dcache.demand_hits 26307388 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 17996874000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.036490 # miss rate for demand accesses +system.cpu.dcache.demand_misses 996300 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 15010432000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.036491 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 996344 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 15007974000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.036490 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 996300 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.874740 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 3582.934837 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.874745 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 3582.956819 # Average occupied blocks per context system.cpu.dcache.overall_accesses 27303688 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18065.511510 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 15065.511510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 18063.709726 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 15063.709726 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 26307344 # number of overall hits -system.cpu.dcache.overall_miss_latency 17999464000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.036491 # miss rate for overall accesses -system.cpu.dcache.overall_misses 996344 # number of overall misses +system.cpu.dcache.overall_hits 26307388 # number of overall hits +system.cpu.dcache.overall_miss_latency 17996874000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.036490 # miss rate for overall accesses +system.cpu.dcache.overall_misses 996300 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 15010432000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.036491 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 996344 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 15007974000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.036490 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 996300 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 942711 # number of replacements system.cpu.dcache.sampled_refs 946807 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3582.934837 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3582.956819 # Cycle average of tags in use system.cpu.dcache.total_refs 26356881 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 54489025000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 96053 # number of writebacks +system.cpu.dcache.warmup_cycle 54487870000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 96132 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 599 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.249734 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 511.454894 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.249735 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 511.457636 # Average occupied blocks per context system.cpu.icache.overall_accesses 107819118 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 54667.779633 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 51667.779633 # average overall mshr miss latency @@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 2 # number of replacements system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 511.454894 # Cycle average of tags in use +system.cpu.icache.tagsinuse 511.457636 # Cycle average of tags in use system.cpu.icache.total_refs 107818519 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -150,12 +150,13 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 46609 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2423668000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 46609 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1864360000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 46609 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2423512000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.999936 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 46606 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1864240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999936 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 46606 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 900797 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency @@ -166,20 +167,20 @@ system.cpu.l2cache.ReadReq_misses 878 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 35120000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.000975 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 878 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 49537 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 49493 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2575924000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 2573636000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 49537 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1981480000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 49493 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1979720000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 49537 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 96053 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 96053 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 49493 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 96132 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 96132 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 52.567404 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 52.533433 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -188,44 +189,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 947406 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 899919 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2469324000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.050123 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 47487 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 899922 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 2469168000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.050120 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 47484 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1899480000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.050123 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 47487 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1899360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.050120 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 47484 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.009182 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.265752 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 300.880505 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 8708.164911 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.009784 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.265384 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 320.609441 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 8696.109935 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 947406 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 899919 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2469324000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.050123 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 47487 # number of overall misses +system.cpu.l2cache.overall_hits 899922 # number of overall hits +system.cpu.l2cache.overall_miss_latency 2469168000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.050120 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 47484 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1899480000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.050123 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 47487 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1899360000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.050120 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 47484 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 678 # number of replacements -system.cpu.l2cache.sampled_refs 15333 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 15344 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 9009.045417 # Cycle average of tags in use -system.cpu.l2cache.total_refs 806016 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 9016.719375 # Cycle average of tags in use +system.cpu.l2cache.total_refs 806073 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 35 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 304316144 # number of cpu cycles simulated +system.cpu.numCycles 304311052 # number of cpu cycles simulated system.cpu.num_insts 91176087 # Number of instructions executed system.cpu.num_refs 27330336 # Number of memory references system.cpu.workload.PROG:num_syscalls 442 # Number of system calls |