summaryrefslogtreecommitdiff
path: root/tests/long/10.mcf/ref/sparc/linux/simple-timing
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2007-03-29 17:39:34 -0500
committerGabe Black <gblack@eecs.umich.edu>2007-03-29 17:39:34 -0500
commit85c1e89444c1c99c80615c6f50ceec03fd30564f (patch)
tree39e3194484884cbd985d05584bf4de7197bbba23 /tests/long/10.mcf/ref/sparc/linux/simple-timing
parent5c4cc4b55271a39789b01565da073332677ae1bb (diff)
downloadgem5-85c1e89444c1c99c80615c6f50ceec03fd30564f.tar.xz
Added a SPARC_SE simple timing mcf regression.
--HG-- extra : convert_revision : d8fea11c37bd3f0b5f5e8880c92b711892ee8125
Diffstat (limited to 'tests/long/10.mcf/ref/sparc/linux/simple-timing')
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini187
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out178
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt230
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out3092
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr7
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout33
6 files changed, 3727 insertions, 0 deletions
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
new file mode 100644
index 000000000..dfb81664a
--- /dev/null
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -0,0 +1,187 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+system=system
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/lgred/input/mcf.in
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out
new file mode 100644
index 000000000..e5ed0b288
--- /dev/null
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out
@@ -0,0 +1,178 @@
+[root]
+type=Root
+dummy=0
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+input=/dist/m5/cpu2000/data/mcf/lgred/input/mcf.in
+output=cout
+env=
+cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
new file mode 100644
index 000000000..b11288b2d
--- /dev/null
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
@@ -0,0 +1,230 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 446147 # Simulator instruction rate (inst/s)
+host_mem_usage 154148 # Number of bytes of host memory used
+host_seconds 3854.32 # Real time elapsed on the host
+host_tick_rate 13681801 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1719594534 # Number of instructions simulated
+sim_seconds 0.052734 # Number of seconds simulated
+sim_ticks 52734070003 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 607807189 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3420.154300 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2420.154300 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 594739458 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 44693656366 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.021500 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 13067731 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 31625925366 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.021500 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 13067731 # number of ReadReq MSHR misses
+system.cpu.dcache.SwapReq_accesses 15448 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_avg_miss_latency 3631.818182 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2631.818182 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits 15437 # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency 39950 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate 0.000712 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses 11 # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency 28950 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate 0.000712 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses 11 # number of SwapReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 166970997 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3255.499606 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2255.499606 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 165264000 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 5557128061 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.010223 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1706997 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 3850131061 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.010223 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1706997 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 51.440428 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 774778186 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3401.130933 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2401.130933 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 760003458 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 50250784427 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.019070 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 14774728 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 35476056427 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.019070 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 14774728 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 774778186 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3401.130933 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2401.130933 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 760003458 # number of overall hits
+system.cpu.dcache.overall_miss_latency 50250784427 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.019070 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 14774728 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 35476056427 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.019070 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 14774728 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 14770643 # number of replacements
+system.cpu.dcache.sampled_refs 14774739 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4094.978951 # Cycle average of tags in use
+system.cpu.dcache.total_refs 760018895 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 35437000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 4191356 # number of writebacks
+system.cpu.icache.ReadReq_accesses 1719594535 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 4032.295228 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 3032.295228 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1719593634 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 3633098 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 901 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 2732098 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 901 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 1908538.994451 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 1719594535 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 4032.295228 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 3032.295228 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1719593634 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 3633098 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
+system.cpu.icache.demand_misses 901 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 2732098 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 901 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 1719594535 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 4032.295228 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 3032.295228 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 1719593634 # number of overall hits
+system.cpu.icache.overall_miss_latency 3633098 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
+system.cpu.icache.overall_misses 901 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 2732098 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 901 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 31 # number of replacements
+system.cpu.icache.sampled_refs 901 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 750.163929 # Cycle average of tags in use
+system.cpu.icache.total_refs 1719593634 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 14775639 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3097.556051 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1926.730191 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 8592784 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 19151739918 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.418449 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 6182855 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 11912693395 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.418449 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 6182855 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 4191356 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 4164131 # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate 0.006496 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 27225 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 0.006496 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 27225 # number of Writeback MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 2.063273 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 14775639 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3097.556051 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1926.730191 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 8592784 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 19151739918 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.418449 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 6182855 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 11912693395 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.418449 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 6182855 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 18966995 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3083.976361 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1926.730191 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 12756915 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 19151739918 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.327415 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 6210080 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 11912693395 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.325980 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 6182855 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 6150087 # number of replacements
+system.cpu.l2cache.sampled_refs 6182855 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 27594.660688 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 12756915 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 12316534000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1069081 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 52734070003 # number of cpu cycles simulated
+system.cpu.num_insts 1719594534 # Number of instructions executed
+system.cpu.num_refs 774793634 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 632 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out
new file mode 100644
index 000000000..6bbb02cf0
--- /dev/null
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out
@@ -0,0 +1,3092 @@
+()
+1642
+***
+1759
+()
+1641
+***
+1691
+()
+1640
+()
+1639
+()
+1638
+()
+1637
+()
+1636
+()
+1635
+()
+1634
+()
+1633
+()
+1632
+()
+1631
+()
+1630
+()
+1629
+()
+1628
+()
+1627
+()
+1626
+()
+1625
+***
+1784
+()
+1624
+()
+1623
+()
+1622
+***
+1688
+()
+1621
+()
+1618
+()
+1617
+***
+1796
+()
+1616
+()
+1615
+***
+1668
+()
+1614
+()
+1613
+()
+1612
+***
+1700
+()
+1611
+()
+1610
+()
+1608
+()
+1606
+()
+1605
+()
+1604
+()
+1603
+()
+1602
+()
+1601
+()
+1599
+()
+1598
+***
+1714
+()
+1597
+()
+1595
+()
+1591
+()
+1590
+***
+1773
+()
+1589
+()
+1588
+()
+1587
+***
+1710
+()
+1586
+()
+1585
+()
+1584
+***
+1748
+()
+1583
+***
+1648
+()
+1582
+()
+1581
+***
+1757
+()
+1579
+()
+1578
+***
+1726
+()
+1575
+***
+1763
+()
+1574
+()
+1573
+()
+1572
+()
+1571
+()
+1568
+()
+1567
+()
+1565
+***
+1643
+()
+1564
+()
+1563
+()
+1562
+()
+1559
+()
+1557
+()
+1556
+()
+1555
+()
+1554
+()
+1553
+***
+1684
+()
+1552
+()
+1551
+***
+1697
+()
+1549
+()
+1546
+***
+1768
+()
+1544
+***
+1798
+()
+1542
+()
+1541
+***
+1650
+()
+1540
+()
+1539
+()
+1538
+()
+1536
+()
+1534
+()
+1533
+()
+1532
+()
+1529
+()
+1528
+()
+1527
+()
+1526
+()
+1525
+()
+1524
+***
+1736
+()
+1523
+()
+1522
+***
+1794
+()
+1521
+()
+1519
+()
+1517
+***
+1687
+()
+1516
+()
+1515
+()
+1514
+()
+1513
+()
+1512
+()
+1511
+()
+1510
+()
+1509
+()
+1508
+()
+1507
+()
+1506
+()
+1505
+()
+1504
+()
+1503
+()
+1502
+***
+1746
+()
+1501
+***
+1766
+()
+1498
+()
+1497
+()
+1495
+()
+1494
+()
+1493
+***
+1673
+()
+1490
+***
+1774
+()
+1486
+()
+1485
+()
+1482
+()
+1481
+()
+1480
+()
+1479
+()
+1477
+()
+1476
+()
+1475
+()
+1473
+()
+1472
+()
+1471
+***
+1728
+()
+1470
+()
+1469
+()
+1467
+()
+1466
+()
+1465
+()
+1464
+()
+1463
+()
+1462
+()
+1461
+()
+1460
+()
+1459
+()
+1455
+()
+1454
+***
+1782
+()
+1453
+()
+1452
+()
+1451
+()
+1449
+***
+1732
+()
+1448
+()
+1445
+()
+1444
+()
+1442
+()
+1441
+()
+1440
+()
+1438
+()
+1437
+()
+1435
+()
+1433
+()
+1432
+***
+1665
+()
+1431
+()
+1426
+()
+1425
+()
+1424
+()
+1423
+()
+1420
+***
+1499
+()
+1419
+***
+1457
+***
+1653
+()
+1418
+***
+1577
+***
+1664
+()
+1417
+***
+1489
+()
+1416
+***
+1545
+()
+1415
+***
+1430
+()
+1414
+***
+1434
+()
+1413
+***
+1594
+***
+1735
+()
+1412
+***
+1560
+***
+1724
+()
+1411
+***
+1428
+()
+1404
+***
+1496
+***
+1780
+()
+1403
+***
+1561
+()
+1402
+***
+1548
+()
+1401
+***
+1569
+***
+1792
+()
+1400
+***
+1537
+()
+1399
+***
+1429
+()
+1392
+***
+1580
+()
+1391
+***
+1410
+()
+1390
+***
+1500
+()
+1389
+***
+1483
+()
+1388
+***
+1570
+()
+1387
+***
+1543
+()
+1386
+***
+1558
+()
+1385
+()
+1384
+()
+1382
+***
+1439
+()
+1381
+***
+1677
+()
+1380
+()
+1378
+***
+1397
+()
+1377
+***
+1787
+()
+1376
+***
+1408
+()
+1375
+()
+1374
+()
+1373
+***
+1671
+()
+1372
+()
+1370
+***
+1793
+()
+1369
+()
+1365
+***
+1762
+()
+1346
+()
+1345
+***
+1566
+()
+1344
+***
+1520
+()
+1343
+***
+1492
+()
+1342
+***
+1576
+***
+1656
+()
+1341
+***
+1447
+()
+1340
+***
+1550
+()
+1339
+()
+1338
+()
+1337
+()
+1329
+***
+1336
+()
+1328
+***
+1446
+()
+1327
+***
+1607
+()
+1325
+()
+1324
+()
+1323
+()
+1317
+()
+1315
+()
+1311
+***
+1450
+***
+1720
+()
+1310
+***
+1619
+()
+1309
+***
+1458
+()
+1308
+()
+1307
+***
+1427
+()
+1306
+***
+1364
+***
+1696
+()
+1299
+()
+1297
+***
+1395
+()
+1296
+()
+1295
+***
+1326
+()
+1294
+***
+1371
+()
+1293
+***
+1456
+()
+1292
+***
+1312
+()
+1291
+()
+1290
+***
+1363
+()
+1282
+***
+1592
+()
+1281
+***
+1379
+()
+1280
+***
+1478
+()
+1279
+***
+1436
+()
+1278
+***
+1620
+()
+1277
+***
+1487
+()
+1276
+***
+1288
+()
+1275
+***
+1596
+()
+1274
+***
+1322
+()
+1273
+***
+1305
+***
+1699
+()
+1272
+()
+1271
+***
+1484
+()
+1270
+***
+1518
+()
+1269
+***
+1289
+()
+1268
+***
+1443
+***
+1786
+()
+1265
+()
+1243
+***
+1368
+()
+1242
+()
+1241
+***
+1421
+***
+1749
+()
+1240
+***
+1260
+***
+1678
+()
+1239
+()
+1238
+()
+1236
+***
+1263
+***
+1767
+()
+1235
+()
+1234
+()
+1233
+()
+1232
+***
+1752
+()
+1231
+***
+1791
+()
+1230
+()
+1229
+()
+1228
+***
+1702
+()
+1227
+()
+1226
+()
+1225
+()
+1224
+()
+1223
+()
+1216
+***
+1531
+()
+1215
+***
+1530
+***
+1797
+()
+1214
+***
+1474
+***
+1742
+()
+1213
+***
+1488
+()
+1212
+***
+1298
+***
+1789
+()
+1211
+***
+1491
+()
+1210
+***
+1600
+()
+1209
+***
+1244
+()
+1208
+***
+1609
+***
+1704
+()
+1207
+***
+1237
+()
+1206
+***
+1468
+()
+1205
+***
+1547
+()
+1204
+***
+1246
+()
+1203
+***
+1593
+***
+1734
+()
+1202
+***
+1535
+()
+1200
+()
+1198
+()
+1196
+()
+1195
+()
+1194
+***
+1302
+()
+1192
+()
+1191
+()
+1189
+()
+1188
+()
+1187
+()
+1186
+()
+1183
+()
+1181
+***
+1778
+()
+1179
+()
+1178
+()
+1177
+***
+1645
+()
+1176
+()
+1175
+***
+1318
+***
+1649
+()
+1173
+()
+1172
+()
+1171
+()
+1169
+***
+1654
+()
+1168
+***
+1692
+()
+1167
+()
+1164
+()
+1163
+()
+1162
+***
+1716
+()
+1160
+()
+1159
+***
+1663
+()
+1157
+()
+1156
+()
+1155
+()
+1154
+()
+1153
+()
+1152
+()
+1150
+()
+1149
+()
+1147
+()
+1145
+()
+1143
+***
+1711
+()
+1142
+()
+1141
+()
+1140
+()
+1139
+***
+1755
+()
+1138
+()
+1137
+***
+1218
+()
+1136
+***
+1248
+***
+1670
+()
+1135
+()
+1134
+()
+1133
+***
+1662
+()
+1132
+()
+1131
+()
+1129
+()
+1128
+()
+1127
+()
+1126
+***
+1301
+()
+1125
+()
+1124
+()
+1123
+()
+1122
+()
+1120
+***
+1332
+()
+1119
+***
+1737
+()
+1118
+***
+1718
+()
+1117
+***
+1250
+***
+1658
+()
+1116
+()
+1114
+()
+1113
+()
+1112
+()
+1111
+***
+1772
+()
+1110
+***
+1359
+()
+1109
+()
+1108
+***
+1251
+()
+1106
+()
+1105
+***
+1771
+()
+1104
+()
+1102
+()
+1101
+()
+1100
+()
+1099
+***
+1689
+()
+1098
+()
+1097
+***
+1785
+()
+1096
+***
+1685
+()
+1095
+()
+1094
+()
+1093
+()
+1092
+()
+1091
+()
+1090
+()
+1089
+()
+1088
+()
+1087
+()
+1086
+()
+1085
+()
+1084
+***
+1739
+()
+1083
+***
+1405
+()
+1082
+()
+1081
+()
+1080
+()
+1078
+()
+1077
+()
+1076
+()
+1075
+()
+1074
+()
+1073
+()
+1072
+()
+1071
+()
+1070
+***
+1707
+()
+1069
+***
+1334
+()
+1068
+()
+1066
+()
+1065
+()
+1064
+()
+1063
+()
+1062
+()
+1061
+()
+1060
+()
+1059
+()
+1058
+()
+1057
+***
+1744
+()
+1056
+()
+1055
+()
+1054
+***
+1335
+()
+1052
+***
+1660
+()
+1051
+()
+1050
+()
+1049
+()
+1048
+()
+1047
+()
+1046
+()
+1045
+***
+1357
+()
+1044
+***
+1659
+()
+1043
+()
+1041
+()
+1040
+()
+1039
+()
+1038
+()
+1037
+()
+1036
+()
+1035
+()
+1034
+()
+1033
+***
+1690
+()
+1031
+()
+1030
+()
+1029
+()
+1028
+***
+1675
+()
+1027
+()
+1026
+()
+1025
+***
+1257
+()
+1024
+()
+1023
+()
+1022
+()
+1021
+()
+1020
+()
+1019
+***
+1284
+()
+1018
+()
+1017
+***
+1754
+()
+1016
+()
+1015
+***
+1247
+()
+1014
+()
+1013
+()
+1012
+***
+1319
+()
+1011
+***
+1352
+***
+1651
+()
+1010
+()
+1009
+***
+1705
+()
+1008
+()
+1007
+()
+1006
+()
+1005
+***
+1679
+()
+1004
+()
+1003
+()
+1002
+()
+1001
+()
+1000
+***
+1731
+()
+999
+()
+998
+()
+996
+()
+995
+()
+994
+()
+993
+()
+991
+***
+1799
+()
+990
+()
+989
+()
+987
+()
+986
+()
+985
+()
+984
+()
+983
+***
+1745
+()
+982
+()
+981
+***
+1644
+()
+980
+()
+979
+()
+978
+()
+977
+()
+976
+()
+975
+()
+974
+***
+1222
+()
+973
+()
+972
+()
+971
+()
+970
+()
+968
+()
+967
+()
+966
+()
+965
+***
+1347
+()
+964
+()
+963
+()
+962
+***
+1743
+()
+961
+***
+1719
+()
+960
+***
+1758
+()
+959
+()
+958
+***
+1733
+()
+957
+***
+1775
+()
+956
+()
+955
+()
+954
+()
+953
+()
+952
+***
+1393
+()
+951
+()
+950
+()
+949
+***
+1669
+()
+948
+()
+947
+()
+946
+***
+1681
+()
+944
+***
+1686
+()
+943
+()
+942
+()
+940
+***
+1783
+()
+939
+()
+938
+()
+937
+()
+936
+()
+934
+()
+933
+()
+932
+()
+931
+()
+930
+()
+929
+***
+1713
+()
+928
+***
+1725
+()
+927
+()
+926
+()
+925
+()
+924
+()
+923
+()
+922
+()
+921
+***
+1394
+()
+920
+***
+1741
+()
+919
+***
+1708
+()
+918
+()
+917
+()
+916
+***
+1723
+()
+915
+()
+914
+()
+913
+()
+912
+()
+911
+()
+910
+()
+909
+***
+1795
+()
+908
+()
+907
+()
+906
+()
+905
+()
+904
+()
+903
+***
+1330
+()
+902
+()
+901
+()
+900
+()
+899
+()
+898
+()
+897
+***
+1790
+()
+896
+***
+1652
+()
+895
+***
+1761
+()
+894
+()
+893
+()
+892
+()
+891
+()
+890
+***
+1253
+()
+889
+***
+1698
+()
+888
+()
+887
+()
+885
+()
+884
+***
+1703
+()
+883
+()
+882
+()
+881
+***
+1747
+()
+880
+()
+879
+***
+1647
+()
+878
+***
+1358
+()
+877
+***
+1407
+()
+876
+()
+875
+()
+874
+***
+1283
+()
+873
+***
+1682
+()
+872
+()
+871
+()
+870
+()
+869
+()
+868
+()
+867
+***
+1751
+()
+866
+()
+865
+()
+864
+()
+863
+()
+862
+***
+1753
+()
+861
+()
+860
+()
+859
+()
+858
+***
+1348
+()
+857
+()
+856
+***
+1350
+()
+855
+***
+1252
+()
+854
+()
+853
+***
+1201
+()
+852
+()
+851
+()
+850
+***
+1361
+()
+849
+()
+848
+()
+847
+()
+846
+()
+845
+()
+844
+()
+843
+()
+842
+()
+841
+()
+840
+()
+839
+***
+1360
+()
+838
+()
+837
+()
+836
+()
+835
+()
+834
+()
+833
+***
+1406
+()
+832
+()
+831
+()
+830
+()
+829
+()
+827
+()
+826
+()
+825
+()
+824
+()
+823
+()
+822
+()
+821
+***
+1683
+()
+820
+***
+1672
+()
+819
+()
+818
+***
+1693
+()
+816
+()
+815
+***
+1313
+()
+814
+()
+813
+()
+812
+***
+1727
+()
+811
+()
+810
+()
+809
+()
+808
+()
+806
+()
+805
+***
+1217
+()
+804
+()
+803
+()
+802
+()
+801
+()
+800
+()
+799
+()
+798
+()
+797
+***
+1220
+()
+796
+***
+1788
+()
+795
+()
+794
+***
+1255
+***
+1674
+()
+793
+***
+1740
+()
+792
+()
+791
+***
+1349
+()
+790
+()
+789
+()
+788
+()
+787
+***
+1800
+()
+786
+()
+785
+()
+784
+()
+783
+()
+782
+()
+781
+()
+780
+()
+779
+()
+778
+()
+777
+()
+776
+()
+775
+()
+774
+***
+1331
+()
+773
+()
+772
+***
+1256
+()
+771
+()
+770
+()
+769
+()
+768
+()
+767
+()
+766
+()
+765
+()
+764
+()
+763
+()
+762
+()
+761
+()
+759
+()
+758
+***
+1655
+()
+757
+()
+756
+()
+755
+***
+1760
+()
+754
+()
+753
+()
+752
+()
+751
+***
+1285
+***
+1680
+()
+750
+***
+1261
+()
+749
+()
+748
+()
+747
+()
+746
+()
+745
+***
+1362
+()
+744
+()
+743
+()
+742
+()
+741
+()
+740
+()
+739
+()
+738
+()
+737
+()
+736
+***
+1729
+()
+735
+***
+1769
+()
+734
+()
+733
+()
+732
+***
+1715
+()
+731
+()
+730
+()
+729
+()
+728
+()
+727
+***
+1721
+()
+726
+()
+725
+()
+724
+()
+723
+()
+722
+()
+721
+()
+720
+()
+719
+***
+1770
+()
+718
+()
+717
+()
+716
+()
+715
+()
+714
+()
+713
+()
+712
+()
+711
+***
+1779
+()
+710
+***
+1221
+()
+709
+()
+708
+()
+707
+()
+706
+()
+705
+***
+1661
+()
+704
+()
+703
+()
+702
+()
+701
+***
+1722
+()
+700
+()
+699
+()
+698
+()
+697
+()
+696
+()
+695
+()
+694
+()
+693
+()
+692
+***
+1776
+()
+690
+***
+1254
+()
+689
+***
+1738
+()
+688
+()
+687
+()
+686
+***
+1287
+()
+685
+()
+684
+()
+683
+()
+682
+()
+681
+***
+1666
+()
+680
+()
+679
+()
+678
+()
+677
+()
+676
+()
+675
+()
+674
+***
+1695
+()
+673
+***
+1709
+()
+672
+()
+671
+()
+670
+()
+669
+()
+667
+()
+666
+()
+665
+()
+664
+()
+663
+()
+662
+()
+661
+***
+1730
+()
+660
+()
+659
+()
+658
+()
+657
+()
+656
+()
+655
+()
+654
+()
+653
+()
+652
+()
+651
+()
+650
+()
+649
+()
+648
+()
+647
+()
+594
+610
+622
+()
+588
+()
+584
+601
+615
+***
+1266
+()
+578
+590
+603
+()
+574
+592
+607
+***
+1646
+()
+568
+()
+564
+582
+598
+()
+558
+570
+***
+1351
+***
+1712
+()
+554
+572
+()
+547
+560
+580
+()
+543
+562
+()
+536
+549
+()
+533
+551
+***
+1356
+()
+527
+539
+()
+524
+541
+()
+518
+530
+()
+514
+531
+()
+508
+521
+***
+1657
+()
+503
+523
+()
+498
+***
+1383
+()
+493
+512
+***
+1422
+()
+487
+501
+()
+484
+515
+***
+1354
+***
+1701
+()
+481
+502
+()
+475
+490
+511
+()
+472
+504
+538
+566
+589
+613
+629
+()
+470
+491
+***
+1303
+()
+464
+()
+461
+494
+526
+556
+579
+605
+623
+639
+()
+450
+***
+1355
+()
+438
+483
+516
+545
+569
+596
+616
+633
+()
+426
+471
+506
+535
+559
+586
+608
+627
+643
+***
+1259
+()
+414
+459
+495
+525
+548
+576
+599
+620
+635
+***
+1765
+()
+402
+449
+500
+()
+401
+446
+482
+***
+1258
+()
+391
+418
+434
+455
+()
+388
+435
+469
+()
+384
+407
+429
+454
+()
+378
+406
+447
+467
+()
+376
+423
+457
+***
+1316
+()
+373
+394
+416
+442
+()
+367
+393
+410
+431
+452
+478
+()
+366
+413
+465
+513
+550
+585
+617
+638
+()
+364
+***
+1146
+***
+1750
+()
+363
+411
+445
+()
+359
+396
+***
+1396
+***
+1756
+()
+357
+381
+405
+430
+458
+479
+***
+1353
+()
+351
+368
+()
+350
+389
+***
+1103
+()
+349
+397
+433
+()
+344
+369
+422
+443
+()
+338
+354
+380
+398
+419
+441
+466
+()
+335
+385
+421
+()
+332
+355
+***
+1320
+()
+327
+375
+428
+505
+540
+575
+609
+632
+***
+1321
+()
+326
+341
+***
+1182
+()
+323
+372
+409
+()
+319
+342
+()
+318
+331
+343
+356
+370
+382
+395
+408
+420
+432
+444
+456
+468
+480
+492
+()
+312
+***
+1161
+()
+309
+346
+383
+***
+1366
+()
+308
+***
+1262
+()
+305
+330
+()
+299
+315
+***
+1333
+***
+1676
+()
+293
+317
+()
+289
+296
+334
+371
+***
+1158
+()
+286
+302
+329
+()
+281
+303
+***
+1219
+()
+280
+292
+304
+316
+***
+1264
+()
+275
+290
+()
+270
+291
+()
+265
+278
+***
+1184
+()
+260
+279
+()
+255
+268
+***
+1367
+()
+250
+269
+***
+1165
+()
+245
+***
+1115
+()
+240
+259
+***
+1067
+()
+235
+248
+***
+1199
+***
+1717
+()
+230
+249
+()
+225
+238
+***
+1197
+()
+220
+239
+()
+215
+***
+935
+()
+210
+229
+258
+***
+1193
+()
+205
+***
+988
+()
+200
+219
+()
+195
+***
+1166
+***
+1667
+()
+190
+209
+***
+1079
+***
+1249
+()
+185
+198
+***
+1180
+()
+131
+161
+192
+221
+252
+282
+320
+()
+118
+151
+182
+211
+242
+271
+306
+***
+1398
+()
+112
+127
+140
+***
+1148
+()
+105
+141
+172
+201
+232
+261
+294
+()
+103
+***
+1144
+()
+92
+130
+162
+191
+222
+251
+283
+321
+358
+()
+91
+***
+886
+()
+80
+136
+174
+216
+254
+301
+348
+404
+473
+520
+555
+591
+619
+()
+79
+117
+152
+181
+212
+241
+272
+307
+345
+***
+1267
+()
+78
+116
+***
+1042
+***
+1764
+()
+74
+87
+100
+114
+126
+()
+73
+95
+111
+128
+149
+165
+178
+***
+997
+()
+70
+119
+166
+204
+246
+285
+339
+386
+439
+485
+532
+557
+583
+606
+625
+640
+646
+()
+66
+104
+142
+171
+202
+231
+262
+295
+333
+***
+1286
+()
+62
+86
+108
+124
+139
+159
+175
+188
+***
+1130
+()
+61
+72
+88
+113
+134
+148
+160
+179
+208
+228
+***
+1245
+()
+57
+106
+157
+193
+236
+273
+328
+374
+427
+474
+519
+552
+()
+56
+***
+969
+()
+55
+109
+153
+197
+233
+277
+325
+377
+424
+476
+517
+553
+577
+602
+621
+637
+645
+()
+54
+110
+154
+196
+234
+276
+324
+379
+425
+477
+522
+561
+595
+624
+642
+()
+53
+90
+129
+***
+1190
+()
+52
+***
+941
+()
+50
+59
+75
+99
+121
+137
+150
+169
+***
+945
+***
+1706
+()
+49
+69
+85
+101
+125
+145
+158
+170
+189
+218
+***
+992
+***
+1781
+()
+48
+68
+122
+163
+207
+244
+288
+336
+390
+436
+489
+529
+()
+45
+96
+143
+187
+223
+267
+310
+360
+***
+1409
+()
+41
+60
+82
+98
+115
+138
+155
+168
+180
+199
+()
+39
+67
+123
+164
+206
+243
+287
+337
+392
+437
+488
+534
+571
+604
+630
+()
+36
+43
+***
+1170
+()
+26
+***
+1107
+()
+24
+40
+***
+817
+()
+20
+46
+97
+144
+186
+224
+266
+311
+365
+412
+463
+507
+542
+567
+593
+614
+631
+()
+19
+33
+***
+1185
+***
+1694
+()
+18
+44
+94
+146
+184
+226
+263
+314
+361
+415
+460
+509
+546
+573
+597
+618
+634
+644
+()
+17
+31
+65
+102
+***
+807
+()
+16
+34
+84
+133
+177
+213
+256
+298
+352
+400
+453
+496
+()
+14
+37
+81
+135
+173
+217
+253
+300
+347
+403
+448
+499
+537
+563
+587
+611
+628
+641
+()
+13
+22
+42
+***
+691
+()
+12
+47
+93
+147
+183
+227
+264
+313
+362
+417
+462
+510
+544
+581
+612
+636
+()
+11
+29
+***
+760
+()
+10
+30
+63
+***
+1121
+()
+9
+35
+83
+132
+176
+214
+257
+297
+353
+399
+451
+497
+***
+1304
+()
+8
+25
+64
+***
+828
+()
+7
+23
+51
+89
+***
+1174
+***
+1300
+()
+6
+28
+71
+120
+167
+203
+247
+284
+340
+387
+440
+486
+528
+565
+600
+626
+()
+5
+***
+668
+()
+4
+32
+77
+***
+1032
+()
+3
+15
+38
+76
+***
+1314
+()
+2
+27
+***
+1053
+()
+1
+21
+58
+107
+156
+194
+237
+274
+322
+***
+1151
+***
+1777
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr
new file mode 100644
index 000000000..9c09fd847
--- /dev/null
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr
@@ -0,0 +1,7 @@
+warn: More than two loadable segments in ELF object.
+warn: Ignoring segment @ 0xa2000 length 0x10.
+warn: More than two loadable segments in ELF object.
+warn: Ignoring segment @ 0x0 length 0x0.
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0. Starting simulation...
+warn: Ignoring request to flush register windows.
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
new file mode 100644
index 000000000..7d97093d4
--- /dev/null
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
@@ -0,0 +1,33 @@
+
+MCF SPEC version 1.6.I
+by Andreas Loebel
+Copyright (c) 1998,1999 ZIB Berlin
+All Rights Reserved.
+
+nodes : 1800
+active arcs : 8190
+simplex iterations : 6837
+flow value : 12860044181
+new implicit arcs : 300000
+active arcs : 308190
+simplex iterations : 11843
+flow value : 9360043604
+new implicit arcs : 22787
+active arcs : 330977
+simplex iterations : 11931
+flow value : 9360043512
+checksum : 798014
+optimal
+M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Mar 29 2007 15:41:48
+M5 started Thu Mar 29 15:42:11 2007
+M5 executing on zizzer.eecs.umich.edu
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+Exiting @ tick 52734070003 because target called exit()