diff options
| author | Steve Reinhardt <stever@gmail.com> | 2010-09-09 14:40:19 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2010-09-09 14:40:19 -0400 |
| commit | 9e45ada1718b6df9310757fdc7cd78db4695516f (patch) | |
| tree | c5cc9f2173f36e38addd8ca08e32ac010e56ef73 /tests/long/10.mcf/ref/sparc/linux | |
| parent | 12497284949cb5418e6bc403723c034aee655666 (diff) | |
| download | gem5-9e45ada1718b6df9310757fdc7cd78db4695516f.tar.xz | |
stats: update stats for preceding coherence changes
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
Diffstat (limited to 'tests/long/10.mcf/ref/sparc/linux')
3 files changed, 84 insertions, 81 deletions
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index 4adb0acbf..dbbbea9b7 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -152,14 +152,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing +cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/mcf +executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf gid=100 -input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout index 80c9b27b1..afcf30904 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing/simout +Redirecting stderr to build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:30:29 -M5 executing on SC2B0619 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing +M5 compiled Aug 26 2010 13:03:41 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:06:13 +M5 executing on zizzer +command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +30,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 366435406000 because target called exit() +Exiting @ tick 366433850000 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 5683e9007..14b141378 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 794629 # Simulator instruction rate (inst/s) -host_mem_usage 325576 # Number of bytes of host memory used -host_seconds 306.85 # Real time elapsed on the host -host_tick_rate 1194166006 # Simulator tick rate (ticks/s) +host_inst_rate 994564 # Simulator instruction rate (inst/s) +host_mem_usage 343716 # Number of bytes of host memory used +host_seconds 245.17 # Real time elapsed on the host +host_tick_rate 1494621764 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated -sim_seconds 0.366435 # Number of seconds simulated -sim_ticks 366435406000 # Number of ticks simulated +sim_seconds 0.366434 # Number of seconds simulated +sim_ticks 366433850000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 14009.690242 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.690242 # average ReadReq mshr miss latency @@ -29,15 +29,15 @@ system.cpu.dcache.SwapReq_mshr_miss_latency 424000 # system.cpu.dcache.SwapReq_mshr_miss_rate 0.002059 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 8 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 22806988 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5317928000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.004147 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 94963 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 5033039000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.004147 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 94963 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 55998.672804 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52998.672804 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 22807014 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5316346000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.004145 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 94937 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5031535000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.004145 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 94937 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks. @@ -47,42 +47,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18046.382944 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency -system.cpu.dcache.demand_hits 104134565 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 17826578000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 18045.256400 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 15045.256400 # average overall mshr miss latency +system.cpu.dcache.demand_hits 104134591 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 17824996000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses -system.cpu.dcache.demand_misses 987820 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 987794 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 14863118000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 14861614000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 987820 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 987794 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.871490 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 3569.622607 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.871491 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 3569.628477 # Average occupied blocks per context system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18046.382944 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 18045.256400 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 15045.256400 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 104134565 # number of overall hits -system.cpu.dcache.overall_miss_latency 17826578000 # number of overall miss cycles +system.cpu.dcache.overall_hits 104134591 # number of overall hits +system.cpu.dcache.overall_miss_latency 17824996000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses -system.cpu.dcache.overall_misses 987820 # number of overall misses +system.cpu.dcache.overall_misses 987794 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 14863118000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 14861614000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 987820 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 987794 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 935475 # number of replacements system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3569.622607 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3569.628477 # Cycle average of tags in use system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 134379688000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 94877 # number of writebacks +system.cpu.dcache.warmup_cycle 134378918000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 94947 # number of writebacks system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55904.761905 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905 # average ReadReq mshr miss latency @@ -116,7 +116,7 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.occ_%::0 0.354611 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 726.242454 # Average occupied blocks per context +system.cpu.icache.occ_blocks::0 726.243472 # Average occupied blocks per context system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency @@ -134,7 +134,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 25 # number of replacements system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 726.242454 # Cycle average of tags in use +system.cpu.icache.tagsinuse 726.243472 # Cycle average of tags in use system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -142,12 +142,13 @@ system.cpu.idle_fraction 0 # Pe system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2429128000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 46714 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1868560000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 46714 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2428972000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.999936 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 46711 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1868440000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999936 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 46711 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency @@ -158,20 +159,20 @@ system.cpu.l2cache.ReadReq_misses 1086 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 43440000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001215 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 1086 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 48257 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 48231 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2509364000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 2508012000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 48257 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1930280000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 48231 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1929240000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 48257 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 94877 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 94877 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 48231 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 94947 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 94947 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 51.559226 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 51.538160 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -180,44 +181,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 892653 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2485600000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.050827 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 47800 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 892656 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 2485444000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.050823 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 47797 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1912000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.050827 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 47800 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1911880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.050823 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 47797 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.010976 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.262444 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 359.659901 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 8599.756547 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.011380 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.262199 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 372.883816 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 8591.744977 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 892653 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2485600000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.050827 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 47800 # number of overall misses +system.cpu.l2cache.overall_hits 892656 # number of overall hits +system.cpu.l2cache.overall_miss_latency 2485444000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.050823 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 47797 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1912000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.050827 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 47800 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1911880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.050823 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 47797 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 891 # number of replacements -system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 15566 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8959.416448 # Cycle average of tags in use -system.cpu.l2cache.total_refs 802210 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 8964.628794 # Cycle average of tags in use +system.cpu.l2cache.total_refs 802243 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 41 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 732870812 # number of cpu cycles simulated +system.cpu.numCycles 732867700 # number of cpu cycles simulated system.cpu.num_insts 243835278 # Number of instructions executed system.cpu.num_refs 105711442 # Number of memory references system.cpu.workload.PROG:num_syscalls 443 # Number of system calls |