diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-06-22 15:06:10 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-06-22 15:06:10 -0400 |
| commit | 8e6abaed797d567b4ce009abac63ba19f87efa28 (patch) | |
| tree | 9e906217ff701f768e7c5e0fc7477c7c72cb2df9 /tests/long/10.mcf/ref/sparc | |
| parent | 49490b334af3bc145071a9a81f37012e7693af59 (diff) | |
| download | gem5-8e6abaed797d567b4ce009abac63ba19f87efa28.tar.xz | |
Update of reference outputs. SPARC_SE o3 gzip didn't have reference outputs, mcf has a reduced input size, and most of the other changes are for a change in how branch mispredicts work which makes things more accurate.
--HG--
extra : convert_revision : 33ad6a220945b344d2fc5c6abef8e67467e0c0ec
Diffstat (limited to 'tests/long/10.mcf/ref/sparc')
10 files changed, 1174 insertions, 5369 deletions
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini index 9b8d69888..9cdc13914 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -39,7 +39,7 @@ env= euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/lgred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in output=cout pid=100 ppid=99 @@ -53,7 +53,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out index 8a5c9fd62..b84a9d780 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out @@ -26,7 +26,7 @@ block_size=64 type=LiveProcess cmd=mcf mcf.in executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf -input=/dist/m5/cpu2000/data/mcf/lgred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in output=cout env= cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt index 530572b5d..ed8482fb4 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 686638 # Simulator instruction rate (inst/s) -host_mem_usage 149820 # Number of bytes of host memory used -host_seconds 2504.37 # Real time elapsed on the host -host_tick_rate 343319148 # Simulator tick rate (ticks/s) +host_inst_rate 1151751 # Simulator instruction rate (inst/s) +host_mem_usage 150484 # Number of bytes of host memory used +host_seconds 211.71 # Real time elapsed on the host +host_tick_rate 575874246 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1719594534 # Number of instructions simulated -sim_seconds 0.859797 # Number of seconds simulated -sim_ticks 859797266500 # Number of ticks simulated +sim_insts 243840172 # Number of instructions simulated +sim_seconds 0.121920 # Number of seconds simulated +sim_ticks 121920085500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1719594534 # number of cpu cycles simulated -system.cpu.num_insts 1719594534 # Number of instructions executed -system.cpu.num_refs 774793634 # Number of memory references -system.cpu.workload.PROG:num_syscalls 632 # Number of system calls +system.cpu.numCycles 243840172 # number of cpu cycles simulated +system.cpu.num_insts 243840172 # Number of instructions executed +system.cpu.num_refs 105125191 # Number of memory references +system.cpu.workload.PROG:num_syscalls 428 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out index 6bbb02cf0..095132477 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out @@ -1,3092 +1,999 @@ () -1642 -*** -1759 -() -1641 -*** -1691 -() -1640 -() -1639 -() -1638 -() -1637 -() -1636 -() -1635 -() -1634 -() -1633 -() -1632 -() -1631 -() -1630 -() -1629 -() -1628 -() -1627 -() -1626 -() -1625 -*** -1784 -() -1624 -() -1623 -() -1622 -*** -1688 -() -1621 -() -1618 -() -1617 -*** -1796 -() -1616 -() -1615 -*** -1668 -() -1614 -() -1613 -() -1612 -*** -1700 -() -1611 -() -1610 -() -1608 -() -1606 -() -1605 -() -1604 -() -1603 -() -1602 -() -1601 -() -1599 -() -1598 -*** -1714 -() -1597 -() -1595 -() -1591 -() -1590 -*** -1773 -() -1589 -() -1588 -() -1587 -*** -1710 -() -1586 -() -1585 -() -1584 -*** -1748 -() -1583 -*** -1648 -() -1582 -() -1581 -*** -1757 -() -1579 -() -1578 -*** -1726 -() -1575 -*** -1763 -() -1574 -() -1573 -() -1572 -() -1571 -() -1568 -() -1567 -() -1565 -*** -1643 -() -1564 -() -1563 -() -1562 -() -1559 -() -1557 -() -1556 -() -1555 -() -1554 -() -1553 -*** -1684 -() -1552 -() -1551 -*** -1697 -() -1549 -() -1546 -*** -1768 -() -1544 -*** -1798 -() -1542 -() -1541 -*** -1650 -() -1540 -() -1539 -() -1538 -() -1536 -() -1534 -() -1533 -() -1532 -() -1529 -() -1528 -() -1527 -() -1526 -() -1525 -() -1524 -*** -1736 -() -1523 -() -1522 -*** -1794 -() -1521 -() -1519 -() -1517 -*** -1687 -() -1516 -() -1515 -() -1514 -() -1513 -() -1512 -() -1511 -() -1510 -() -1509 -() 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-1356 -() -527 -539 -() -524 -541 -() -518 -530 -() -514 -531 +254 () -508 -521 +104 *** -1657 -() -503 -523 -() -498 +138 *** -1383 +161 () -493 -512 +103 *** -1422 -() -487 -501 +310 () -484 -515 +102 *** -1354 +223 *** -1701 -() -481 -502 -() -475 -490 -511 -() -472 -504 -538 -566 -589 -613 -629 +252 () -470 -491 -*** -1303 +80 () -464 +70 () -461 -494 -526 -556 -579 -605 -623 -639 +69 () -450 -*** -1355 +68 () -438 -483 -516 -545 -569 -596 -616 -633 +66 () -426 -471 -506 -535 -559 -586 -608 -627 -643 -*** -1259 +64 () -414 -459 -495 -525 -548 -576 -599 -620 -635 +62 *** -1765 -() -402 -449 -500 +256 () -401 -446 -482 +61 *** -1258 -() -391 -418 -434 -455 -() -388 -435 -469 -() -384 -407 -429 -454 -() -378 -406 -447 -467 +93 () -376 -423 -457 +59 *** -1316 -() -373 -394 -416 -442 -() -367 -393 -410 -431 -452 -478 +120 () -366 -413 -465 -513 -550 -585 -617 -638 +58 () -364 -*** -1146 +57 *** -1750 +183 () -363 -411 -445 +55 () -359 -396 -*** -1396 -*** -1756 +54 () -357 -381 -405 -430 -458 -479 +52 *** -1353 -() -351 -368 +147 () -350 -389 +51 *** -1103 -() -349 -397 -433 -() -344 -369 -422 -443 -() -338 -354 -380 -398 -419 -441 -466 -() -335 -385 -421 +118 () -332 -355 +50 *** -1320 +83 () -327 -375 -428 -505 -540 -575 -609 -632 +49 *** -1321 +98 () -326 -341 +48 *** -1182 -() -323 -372 -409 -() -319 -342 -() -318 -331 -343 -356 -370 -382 -395 -408 -420 -432 -444 -456 -468 -480 -492 +99 () -312 -*** -1161 +47 () -309 -346 -383 +46 *** -1366 +184 () -308 +45 *** -1262 +121 () -305 -330 +44 () -299 -315 -*** -1333 +43 *** -1676 -() -293 -317 +88 () -289 -296 -334 -371 +42 *** -1158 -() -286 -302 -329 +122 () -281 -303 +41 *** -1219 +91 () -280 -292 -304 -316 +40 *** -1264 -() -275 -290 -() -270 -291 +96 () -265 -278 +38 *** -1184 -() -260 -279 +100 () -255 -268 +37 *** -1367 +149 () -250 -269 +36 *** -1165 +74 () -245 +35 *** -1115 +258 () -240 -259 +34 *** -1067 +151 () -235 -248 -*** -1199 +33 *** -1717 +85 () -230 -249 +32 () -225 -238 +31 *** -1197 -() -220 -239 +94 () -215 +30 *** -935 +97 () -210 -229 -258 +29 *** -1193 +90 () -205 +28 *** -988 -() -200 -219 +89 () -195 -*** -1166 +27 *** -1667 +92 () -190 -209 -*** -1079 +26 *** -1249 -() -185 -198 +72 *** -1180 -() -131 -161 -192 -221 -252 -282 -320 +247 () -118 -151 -182 -211 -242 -271 -306 +25 *** -1398 +86 () -112 -127 -140 +24 *** -1148 -() -105 -141 -172 -201 -232 -261 -294 +82 () -103 +23 *** -1144 -() -92 -130 -162 -191 -222 -251 -283 -321 -358 -() -91 +87 *** -886 -() -80 -136 -174 -216 -254 -301 -348 -404 -473 -520 -555 -591 -619 -() -79 117 -152 -181 -212 -241 -272 -307 -345 -*** -1267 () -78 -116 -*** -1042 +22 *** -1764 -() -74 -87 -100 -114 -126 -() -73 -95 -111 -128 -149 -165 -178 +76 *** -997 -() -70 119 -166 -204 -246 -285 -339 -386 -439 -485 -532 -557 -583 -606 -625 -640 -646 -() -66 -104 -142 -171 -202 -231 -262 -295 -333 -*** -1286 () -62 -86 -108 -124 -139 -159 -175 -188 +21 *** -1130 +84 () -61 -72 -88 -113 -134 -148 -160 -179 -208 -228 +20 *** -1245 -() -57 -106 -157 -193 -236 -273 -328 -374 -427 -474 -519 -552 +78 () -56 +19 *** -969 -() -55 -109 -153 -197 -233 -277 -325 -377 -424 -476 -517 -553 -577 -602 -621 -637 -645 -() -54 -110 -154 -196 -234 -276 -324 -379 -425 -477 -522 -561 -595 -624 -642 +73 () -53 -90 -129 +18 *** -1190 +81 () -52 +17 *** -941 +65 () -50 -59 -75 -99 -121 -137 -150 -169 +16 *** -945 +63 *** -1706 -() -49 -69 -85 101 -125 -145 -158 -170 -189 -218 -*** -992 -*** -1781 -() -48 -68 -122 -163 -207 -244 -288 -336 -390 -436 -489 -529 -() -45 -96 -143 -187 -223 -267 -310 -360 -*** -1409 -() -41 -60 -82 -98 -115 -138 -155 -168 -180 -199 () -39 -67 -123 -164 -206 -243 -287 -337 -392 -437 -488 -534 -571 -604 -630 -() -36 -43 -*** -1170 -() -26 -*** -1107 -() -24 -40 -*** -817 -() -20 -46 -97 -144 -186 -224 -266 -311 -365 -412 -463 -507 -542 -567 -593 -614 -631 -() -19 -33 -*** -1185 -*** -1694 -() -18 -44 -94 -146 -184 -226 -263 -314 -361 -415 -460 -509 -546 -573 -597 -618 -634 -644 -() -17 -31 -65 -102 +15 *** -807 -() -16 -34 -84 -133 -177 -213 -256 -298 -352 -400 -453 -496 +71 () 14 -37 -81 -135 -173 -217 -253 -300 -347 -403 -448 -499 -537 -563 -587 -611 -628 -641 +*** +75 () 13 -22 -42 *** -691 +322 () 12 -47 -93 -147 -183 -227 -264 -313 -362 -417 -462 -510 -544 -581 -612 -636 +*** +77 () 11 -29 *** -760 +283 () 10 -30 -63 *** -1121 +79 () 9 -35 -83 -132 -176 -214 -257 -297 -353 -399 -451 -497 *** -1304 +145 +*** +150 () 8 -25 -64 *** -828 +67 () 7 -23 -51 -89 *** -1174 +60 *** -1300 +231 () 6 -28 -71 -120 -167 -203 -247 -284 -340 -387 -440 -486 -528 -565 -600 -626 +*** +56 +*** +234 () 5 *** -668 +164 +*** +202 () 4 -32 -77 *** -1032 +53 () 3 -15 -38 -76 *** -1314 +130 +*** +185 +*** +200 () 2 -27 *** -1053 +205 () 1 -21 -58 -107 -156 -194 -237 -274 -322 *** -1151 +39 *** -1777 +95 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout index bd861b307..448df62f5 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout @@ -4,19 +4,15 @@ by Andreas Loebel Copyright (c) 1998,1999 ZIB Berlin All Rights Reserved. -nodes : 1800 -active arcs : 8190 -simplex iterations : 6837 -flow value : 12860044181 -new implicit arcs : 300000 -active arcs : 308190 -simplex iterations : 11843 -flow value : 9360043604 -new implicit arcs : 22787 -active arcs : 330977 -simplex iterations : 11931 -flow value : 9360043512 -checksum : 798014 +nodes : 500 +active arcs : 1905 +simplex iterations : 1502 +flow value : 4990014995 +new implicit arcs : 23867 +active arcs : 25772 +simplex iterations : 2663 +flow value : 3080014995 +checksum : 68389 optimal M5 Simulator System @@ -25,9 +21,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 15 2007 13:02:31 -M5 started Tue May 15 14:23:47 2007 +M5 compiled Jun 21 2007 21:15:48 +M5 started Fri Jun 22 01:58:18 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 859797266500 because target called exit() +Exiting @ tick 121920085500 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index 9beb527ea..fe99eeeb9 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -31,6 +31,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 compressed_bus=false @@ -44,7 +45,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -69,6 +70,7 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.icache] type=BaseCache adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 compressed_bus=false @@ -82,7 +84,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -107,6 +109,7 @@ mem_side=system.cpu.toL2Bus.port[0] [system.cpu.l2cache] type=BaseCache adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 compressed_bus=false @@ -120,7 +123,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -160,7 +163,7 @@ env= euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/lgred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in output=cout pid=100 ppid=99 @@ -174,7 +177,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out index 5d5cc71c1..81e06c995 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out @@ -26,7 +26,7 @@ block_size=64 type=LiveProcess cmd=mcf mcf.in executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf -input=/dist/m5/cpu2000/data/mcf/lgred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in output=cout env= cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing @@ -94,7 +94,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -131,7 +131,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true @@ -168,7 +168,7 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=100000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt index c95331047..56d2d33b9 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,77 +1,77 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 480485 # Simulator instruction rate (inst/s) -host_mem_usage 155316 # Number of bytes of host memory used -host_seconds 3578.87 # Real time elapsed on the host -host_tick_rate 745845171 # Simulator tick rate (ticks/s) +host_inst_rate 697152 # Simulator instruction rate (inst/s) +host_mem_usage 155896 # Number of bytes of host memory used +host_seconds 349.77 # Real time elapsed on the host +host_tick_rate 1027373651 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1719594534 # Number of instructions simulated -sim_seconds 2.669285 # Number of seconds simulated -sim_ticks 2669284585000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 607807189 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 12893.226605 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11893.226605 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 594739458 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 168485217000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.021500 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 13067731 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 155417486000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.021500 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 13067731 # number of ReadReq MSHR misses -system.cpu.dcache.SwapReq_accesses 15448 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 13090.909091 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 12090.909091 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 15437 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 144000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.000712 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 11 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 133000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.000712 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 11 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 166970997 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 12404.292450 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11404.292450 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 165264000 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 21174090000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.010223 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1706997 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 19467093000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010223 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1706997 # number of WriteReq MSHR misses +sim_insts 243840172 # Number of instructions simulated +sim_seconds 0.359341 # Number of seconds simulated +sim_ticks 359340764000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 82219469 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 12000.343864 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11000.343864 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 81326673 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 10713859000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 892796 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 9821063000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 892796 # number of ReadReq MSHR misses +system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_avg_miss_latency 12500 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 3882 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 50000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.001029 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 4 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 46000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.001029 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 4 # number of SwapReq MSHR misses +system.cpu.dcache.WriteReq_accesses 22901836 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 12623.899964 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11623.899964 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 22855133 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 589574000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.002039 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 46703 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 542871000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002039 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 46703 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 51.440428 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 110.894471 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 774778186 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 12836.737637 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 11836.737637 # average overall mshr miss latency -system.cpu.dcache.demand_hits 760003458 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 189659307000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.019070 # miss rate for demand accesses -system.cpu.dcache.demand_misses 14774728 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 105121305 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 12031.341172 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11031.341172 # average overall mshr miss latency +system.cpu.dcache.demand_hits 104181806 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 11303433000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.008937 # miss rate for demand accesses +system.cpu.dcache.demand_misses 939499 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 174884579000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.019070 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 14774728 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 10363934000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.008937 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 939499 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 774778186 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 12836.737637 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 11836.737637 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 105121305 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 12031.341172 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11031.341172 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 760003458 # number of overall hits -system.cpu.dcache.overall_miss_latency 189659307000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.019070 # miss rate for overall accesses -system.cpu.dcache.overall_misses 14774728 # number of overall misses +system.cpu.dcache.overall_hits 104181806 # number of overall hits +system.cpu.dcache.overall_miss_latency 11303433000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.008937 # miss rate for overall accesses +system.cpu.dcache.overall_misses 939499 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 174884579000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.019070 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 14774728 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 10363934000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.008937 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 939499 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -83,57 +83,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 14770643 # number of replacements -system.cpu.dcache.sampled_refs 14774739 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 935407 # number of replacements +system.cpu.dcache.sampled_refs 939503 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.628585 # Cycle average of tags in use -system.cpu.dcache.total_refs 760018895 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3913237000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 4191356 # number of writebacks -system.cpu.icache.ReadReq_accesses 1719594535 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 13991.120977 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12991.120977 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1719593634 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 12606000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 901 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 11705000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 901 # number of ReadReq MSHR misses +system.cpu.dcache.tagsinuse 3560.887601 # Cycle average of tags in use +system.cpu.dcache.total_refs 104185688 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 134116230000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 94807 # number of writebacks +system.cpu.icache.ReadReq_accesses 243840173 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 13993.174061 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12993.174061 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 243839294 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 12300000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 879 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 11421000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 879 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1908538.994451 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 277405.340159 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1719594535 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 13991.120977 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12991.120977 # average overall mshr miss latency -system.cpu.icache.demand_hits 1719593634 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 12606000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.demand_misses 901 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 243840173 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 13993.174061 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12993.174061 # average overall mshr miss latency +system.cpu.icache.demand_hits 243839294 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 12300000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses +system.cpu.icache.demand_misses 879 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11705000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 901 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 11421000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 879 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1719594535 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 13991.120977 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12991.120977 # average overall mshr miss latency +system.cpu.icache.overall_accesses 243840173 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 13993.174061 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12993.174061 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1719593634 # number of overall hits -system.cpu.icache.overall_miss_latency 12606000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.overall_misses 901 # number of overall misses +system.cpu.icache.overall_hits 243839294 # number of overall hits +system.cpu.icache.overall_miss_latency 12300000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses +system.cpu.icache.overall_misses 879 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11705000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 901 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 11421000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 879 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -145,64 +145,60 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 31 # number of replacements -system.cpu.icache.sampled_refs 901 # Sample count of references to valid blocks. +system.cpu.icache.replacements 25 # number of replacements +system.cpu.icache.sampled_refs 879 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 737.715884 # Cycle average of tags in use -system.cpu.icache.total_refs 1719593634 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 716.200092 # Cycle average of tags in use +system.cpu.icache.total_refs 243839294 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 14775639 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 12999.785859 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.785859 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 8592784 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 80375791000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.418449 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 6182855 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 68010081000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.418449 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 6182855 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 4191356 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 4164131 # number of Writeback hits -system.cpu.l2cache.Writeback_miss_rate 0.006496 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 27225 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 0.006496 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 27225 # number of Writeback MSHR misses +system.cpu.l2cache.ReadReq_accesses 940381 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 924777 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 202852000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.016593 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 15604 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 171644000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.016593 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 15604 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 94807 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 94807 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.063273 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 65.341195 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 14775639 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 12999.785859 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.785859 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 8592784 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 80375791000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.418449 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 6182855 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 940381 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 924777 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 202852000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.016593 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 15604 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 68010081000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.418449 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 6182855 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 171644000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.016593 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 15604 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 18966995 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 12942.794779 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.785859 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 1035188 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 12756915 # number of overall hits -system.cpu.l2cache.overall_miss_latency 80375791000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.327415 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 6210080 # number of overall misses +system.cpu.l2cache.overall_hits 1019584 # number of overall hits +system.cpu.l2cache.overall_miss_latency 202852000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.015074 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 15604 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 68010081000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.325980 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 6182855 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 171644000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.015074 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 15604 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -214,17 +210,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 6150087 # number of replacements -system.cpu.l2cache.sampled_refs 6182855 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 15604 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 26129.060966 # Cycle average of tags in use -system.cpu.l2cache.total_refs 12756915 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 806915893000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1069081 # number of writebacks +system.cpu.l2cache.tagsinuse 10833.027960 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1019584 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2669284585000 # number of cpu cycles simulated -system.cpu.num_insts 1719594534 # Number of instructions executed -system.cpu.num_refs 774793634 # Number of memory references -system.cpu.workload.PROG:num_syscalls 632 # Number of system calls +system.cpu.numCycles 359340764000 # number of cpu cycles simulated +system.cpu.num_insts 243840172 # Number of instructions executed +system.cpu.num_refs 105125191 # Number of memory references +system.cpu.workload.PROG:num_syscalls 428 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out index 6bbb02cf0..095132477 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out @@ -1,3092 +1,999 @@ () -1642 -*** -1759 -() -1641 -*** -1691 -() -1640 -() -1639 -() -1638 -() -1637 -() -1636 -() -1635 -() -1634 -() -1633 -() -1632 -() -1631 -() -1630 -() -1629 -() -1628 -() -1627 -() -1626 -() -1625 -*** -1784 -() -1624 -() -1623 -() -1622 -*** -1688 -() -1621 -() -1618 -() -1617 -*** -1796 -() -1616 -() -1615 -*** -1668 -() -1614 -() -1613 -() -1612 -*** -1700 -() -1611 -() -1610 -() -1608 -() -1606 -() -1605 -() -1604 -() -1603 -() -1602 -() -1601 -() -1599 -() -1598 -*** -1714 -() -1597 -() -1595 -() -1591 -() -1590 -*** -1773 -() -1589 -() -1588 -() -1587 -*** -1710 -() -1586 -() -1585 -() -1584 -*** -1748 -() -1583 -*** -1648 -() -1582 -() -1581 -*** -1757 -() -1579 -() -1578 -*** -1726 -() -1575 -*** -1763 -() -1574 -() -1573 -() -1572 -() -1571 -() -1568 -() -1567 -() -1565 -*** -1643 -() -1564 -() -1563 -() -1562 -() -1559 -() -1557 -() -1556 -() -1555 -() -1554 -() -1553 -*** -1684 -() -1552 -() -1551 -*** -1697 -() -1549 -() -1546 -*** -1768 -() -1544 -*** -1798 -() -1542 -() -1541 -*** -1650 -() -1540 -() -1539 -() -1538 -() -1536 -() -1534 -() -1533 -() -1532 -() -1529 -() -1528 -() -1527 -() -1526 -() -1525 -() -1524 -*** -1736 -() -1523 -() -1522 -*** -1794 -() -1521 -() -1519 -() -1517 -*** -1687 -() -1516 -() -1515 -() -1514 -() -1513 -() -1512 -() -1511 -() -1510 -() -1509 -() -1508 -() -1507 -() -1506 -() -1505 -() -1504 -() -1503 -() -1502 -*** -1746 -() -1501 -*** -1766 -() -1498 -() -1497 -() -1495 -() -1494 -() -1493 -*** -1673 -() -1490 -*** -1774 -() -1486 -() -1485 -() -1482 -() -1481 -() -1480 -() -1479 -() -1477 -() -1476 -() -1475 -() -1473 -() -1472 -() -1471 -*** -1728 -() -1470 -() -1469 -() -1467 -() -1466 -() -1465 -() -1464 -() -1463 -() -1462 -() -1461 -() -1460 -() -1459 -() -1455 -() -1454 -*** -1782 -() -1453 -() -1452 -() -1451 -() -1449 -*** -1732 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-247 -284 -340 -387 -440 -486 -528 -565 -600 -626 +*** +56 +*** +234 () 5 *** -668 +164 +*** +202 () 4 -32 -77 *** -1032 +53 () 3 -15 -38 -76 *** -1314 +130 +*** +185 +*** +200 () 2 -27 *** -1053 +205 () 1 -21 -58 -107 -156 -194 -237 -274 -322 *** -1151 +39 *** -1777 +95 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout index 272fc2ce1..51a3ec215 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout @@ -4,19 +4,15 @@ by Andreas Loebel Copyright (c) 1998,1999 ZIB Berlin All Rights Reserved. -nodes : 1800 -active arcs : 8190 -simplex iterations : 6837 -flow value : 12860044181 -new implicit arcs : 300000 -active arcs : 308190 -simplex iterations : 11843 -flow value : 9360043604 -new implicit arcs : 22787 -active arcs : 330977 -simplex iterations : 11931 -flow value : 9360043512 -checksum : 798014 +nodes : 500 +active arcs : 1905 +simplex iterations : 1502 +flow value : 4990014995 +new implicit arcs : 23867 +active arcs : 25772 +simplex iterations : 2663 +flow value : 3080014995 +checksum : 68389 optimal M5 Simulator System @@ -25,9 +21,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 15 2007 13:02:31 -M5 started Tue May 15 15:05:32 2007 +M5 compiled Jun 21 2007 21:15:48 +M5 started Fri Jun 22 02:01:52 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2669284585000 because target called exit() +Exiting @ tick 359340764000 because target called exit() |