diff options
author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
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committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
commit | 13a15c55a40e86e5f3948a387fb5e50b9a1cdccf (patch) | |
tree | 762286677b3170cf9a7fb348f44e74a276230d6c /tests/long/10.mcf/ref/x86/linux/simple-timing/simout | |
parent | e9185363804489ce2b84d50fe77ed94f3a5f1e01 (diff) | |
download | gem5-13a15c55a40e86e5f3948a387fb5e50b9a1cdccf.tar.xz |
stats: update stats for previous cset
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
Diffstat (limited to 'tests/long/10.mcf/ref/x86/linux/simple-timing/simout')
-rwxr-xr-x | tests/long/10.mcf/ref/x86/linux/simple-timing/simout | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index 243f7ada9..7070284ed 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simout -Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:20:12 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:47:25 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:49 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:29:54 +M5 executing on phenom command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -30,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 378879619000 because target called exit() +Exiting @ tick 370010840000 because target called exit() |