diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
| commit | 13a15c55a40e86e5f3948a387fb5e50b9a1cdccf (patch) | |
| tree | 762286677b3170cf9a7fb348f44e74a276230d6c /tests/long/10.mcf/ref/x86 | |
| parent | e9185363804489ce2b84d50fe77ed94f3a5f1e01 (diff) | |
| download | gem5-13a15c55a40e86e5f3948a387fb5e50b9a1cdccf.tar.xz | |
stats: update stats for previous cset
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
Diffstat (limited to 'tests/long/10.mcf/ref/x86')
3 files changed, 96 insertions, 107 deletions
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini index a75b06e16..b40b0b08f 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -157,9 +157,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index 243f7ada9..7070284ed 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simout -Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:20:12 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:47:25 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:49 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:29:54 +M5 executing on phenom command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -30,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 378879619000 because target called exit() +Exiting @ tick 370010840000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index 951737b71..5a6f923f1 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1022159 # Simulator instruction rate (inst/s) -host_mem_usage 344728 # Number of bytes of host memory used -host_seconds 263.85 # Real time elapsed on the host -host_tick_rate 1435967954 # Simulator tick rate (ticks/s) +host_inst_rate 1130440 # Simulator instruction rate (inst/s) +host_mem_usage 330088 # Number of bytes of host memory used +host_seconds 238.58 # Real time elapsed on the host +host_tick_rate 1550911771 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 269696010 # Number of instructions simulated -sim_seconds 0.378880 # Number of seconds simulated -sim_ticks 378879619000 # Number of ticks simulated +sim_seconds 0.370011 # Number of seconds simulated +sim_ticks 370010840000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 15327.890775 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12327.890775 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 88818730 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 30053702000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 28849058000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.021599 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 1960720 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24171542000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 22966898000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1960720 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55478.946733 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52478.946733 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 31241017 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 11025553000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.006321 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 198734 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 10429351000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006321 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 198734 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 31333642 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3268793000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.003375 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 106109 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 2950464500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003375 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 106109 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 122219201 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 19022.982198 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 16022.982198 # average overall mshr miss latency -system.cpu.dcache.demand_hits 120059747 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 41079255000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.017669 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2159454 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 15539.675029 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency +system.cpu.dcache.demand_hits 120152372 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 32117851000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.016911 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2066829 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 34600893000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.017669 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2159454 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 25917362500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.016911 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2066829 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995362 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4077.003489 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.995279 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 19022.982198 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 16022.982198 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 120059747 # number of overall hits -system.cpu.dcache.overall_miss_latency 41079255000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.017669 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2159454 # number of overall misses +system.cpu.dcache.overall_hits 120152372 # number of overall hits +system.cpu.dcache.overall_miss_latency 32117851000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.016911 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2066829 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 34600893000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.017669 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2159454 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 25917362500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.016911 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2066829 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 2062733 # number of replacements system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4077.003489 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 127444032000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 283281 # number of writebacks +system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 1437080 # number of writebacks system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 808 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.325684 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 667.001102 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.325289 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -124,91 +124,82 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 667.001102 # Cycle average of tags in use +system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 106109 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.299104 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 2466 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 5389467000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.976760 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 103643 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4145720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.976760 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 103643 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 63651 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2207845500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.400136 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 42458 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1698320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.400136 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 42458 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 1961528 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1898729 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3265548000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.032015 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 62799 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 2511960000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.032015 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 62799 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 92625 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51994.385965 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 4815980000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 92625 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3705000000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 92625 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 283281 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 283281 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 1927411 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1774084000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.017393 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 34117 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1364680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017393 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 34117 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 1437080 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1437080 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 19.797170 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 2067637 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000.186251 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000.385243 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1901195 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 8655015000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.080499 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 166442 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 1991062 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3981929500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.037035 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 76575 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 6657680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.080499 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 166442 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 3063000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.037035 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 76575 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.204822 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.350671 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 6711.601001 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 11490.800356 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.199945 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.368128 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000.186251 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1901195 # number of overall hits -system.cpu.l2cache.overall_miss_latency 8655015000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.080499 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 166442 # number of overall misses +system.cpu.l2cache.overall_hits 1991062 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3981929500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.037035 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 76575 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 6657680000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.080499 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 166442 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 3063000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.037035 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 76575 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 81066 # number of replacements -system.cpu.l2cache.sampled_refs 106133 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 49212 # number of replacements +system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18202.401357 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2101133 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 48460 # number of writebacks +system.cpu.l2cache.writebacks 29460 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 757759238 # number of cpu cycles simulated +system.cpu.numCycles 740021680 # number of cpu cycles simulated system.cpu.num_insts 269696010 # Number of instructions executed system.cpu.num_refs 122219139 # Number of memory references system.cpu.workload.PROG:num_syscalls 444 # Number of system calls |