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authorAli Saidi <saidi@eecs.umich.edu>2011-09-13 12:58:09 -0400
committerAli Saidi <saidi@eecs.umich.edu>2011-09-13 12:58:09 -0400
commit28a2236ec18e3d5a82d6f7caffbf8285aec48b38 (patch)
treebfd2d8d78733f95b30e9f671229ce2f0f55f4d94 /tests/long/10.mcf/ref/x86
parent649c239ceef2d107fae253b1008c6f214f242d73 (diff)
downloadgem5-28a2236ec18e3d5a82d6f7caffbf8285aec48b38.tar.xz
O3: Update stats for new ordering fix.
Diffstat (limited to 'tests/long/10.mcf/ref/x86')
-rw-r--r--tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini4
-rwxr-xr-xtests/long/10.mcf/ref/x86/linux/o3-timing/simout8
-rw-r--r--tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt722
3 files changed, 367 insertions, 367 deletions
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
index aaea60ae0..df2fb6f73 100644
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -500,9 +500,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/x86/linux/mcf
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/arm/scratch/sysexplr/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
index 796b5db5e..d1aeffbca 100755
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 17 2011 17:25:41
-gem5 started Aug 17 2011 17:30:37
-gem5 executing on nadc-0388
+gem5 compiled Aug 20 2011 13:24:14
+gem5 started Aug 20 2011 13:24:28
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -25,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 71354418000 because target called exit()
+Exiting @ tick 70374234500 because target called exit()
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 542fef85a..f17fe7434 100644
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,251 +1,251 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.071354 # Number of seconds simulated
-sim_ticks 71354418000 # Number of ticks simulated
+sim_seconds 0.070374 # Number of seconds simulated
+sim_ticks 70374234500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 121216 # Simulator instruction rate (inst/s)
-host_tick_rate 31091054 # Simulator tick rate (ticks/s)
-host_mem_usage 393776 # Number of bytes of host memory used
-host_seconds 2295.01 # Real time elapsed on the host
+host_inst_rate 169063 # Simulator instruction rate (inst/s)
+host_tick_rate 42767879 # Simulator tick rate (ticks/s)
+host_mem_usage 346452 # Number of bytes of host memory used
+host_seconds 1645.49 # Real time elapsed on the host
sim_insts 278192519 # Number of instructions simulated
system.cpu.workload.num_syscalls 444 # Number of system calls
-system.cpu.numCycles 142708837 # number of cpu cycles simulated
+system.cpu.numCycles 140748470 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 38713050 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 38713050 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1277784 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 34149959 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 33632947 # Number of BTB hits
+system.cpu.BPredUnit.lookups 37906853 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 37906853 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1330176 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 33468761 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 32955372 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 29563972 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 207959070 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 38713050 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 33632947 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 64671203 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 11251281 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 37585887 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 29094074 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 203757407 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 37906853 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 32955372 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 63225813 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 10352620 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 38317432 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 97 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 28742973 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 228078 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 141556039 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.590408 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.296325 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 28270666 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 203655 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 139622279 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.575042 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.293353 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 79448784 56.13% 56.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3733414 2.64% 58.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2922001 2.06% 60.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 4489594 3.17% 64.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 6936058 4.90% 68.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 5469177 3.86% 72.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 7685058 5.43% 78.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 4534397 3.20% 81.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 26337556 18.61% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 78878326 56.49% 56.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3468234 2.48% 58.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2811542 2.01% 60.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 4524513 3.24% 64.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 6755323 4.84% 69.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 5317016 3.81% 72.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 7687744 5.51% 78.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 4301095 3.08% 81.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 25878486 18.53% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 141556039 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.271273 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.457226 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 42383946 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 28100231 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 53949523 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 7387481 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 9734858 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 362029152 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 9734858 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 49345988 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 4251907 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 6895 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 54198746 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 24017645 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 357077595 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 112284 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 20035490 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 320906324 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 879462898 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 879458894 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4004 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 139622279 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.269323 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.447670 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 41959628 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 28656621 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 52572729 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 7448460 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 8984841 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 355072137 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 8984841 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 48879402 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 4457870 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 6893 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 52910993 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 24382280 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 350563031 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 104227 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 20384891 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 314779048 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 862154595 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 862151489 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 3106 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 72562132 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 66434856 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 479 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 472 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 56213524 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 115636696 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 38304742 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 48747327 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 8476101 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 349796606 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 465 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 319480009 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 127874 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 71460780 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 105775967 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 141556039 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.256915 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.760467 # Number of insts issued each cycle
+system.cpu.rename.skidInsts 56483579 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 112824537 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 37669092 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 48262856 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 8162457 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 343955075 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 466 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 316373550 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 98329 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 65563048 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 93813941 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 139622279 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.265925 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.753143 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 32928700 23.26% 23.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 18859354 13.32% 36.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 25409770 17.95% 54.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 30153045 21.30% 75.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 18699176 13.21% 89.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 10380312 7.33% 96.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 3284045 2.32% 98.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1793650 1.27% 99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 47987 0.03% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 31939796 22.88% 22.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 18447556 13.21% 36.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 25584563 18.32% 54.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 29944678 21.45% 75.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 18447649 13.21% 89.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 10291416 7.37% 96.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 3138355 2.25% 98.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1781100 1.28% 99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 47166 0.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 141556039 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 139622279 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 25871 1.36% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1792047 94.50% 95.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 78518 4.14% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 26426 1.39% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1802884 94.84% 96.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 71697 3.77% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 181286722 56.74% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 231 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.75% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 103851207 32.51% 89.26% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 34325138 10.74% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 180370396 57.01% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 163 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 101485830 32.08% 89.10% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 34500450 10.90% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 319480009 # Type of FU issued
-system.cpu.iq.rate 2.238684 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1896436 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.005936 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 782539275 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 421630860 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 314706696 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 1092 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 2558 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 444 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 321359193 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 541 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 45621060 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 316373550 # Type of FU issued
+system.cpu.iq.rate 2.247794 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1901007 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006009 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 774367858 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 409550255 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 312670753 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 857 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1937 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 344 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 318257421 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 425 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 45906074 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 24857308 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 124101 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 396603 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 6864991 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 22045149 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 125133 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 34222 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 6229341 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2744 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 15359 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2799 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 15405 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 9734858 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 919734 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 96297 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 349797071 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 26061 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 115636696 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 38304742 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 6174 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 48786 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 396603 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1201294 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 194628 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1395922 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 317091801 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 103103021 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2388208 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 8984841 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 901233 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 88686 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 343955541 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 25713 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 112824537 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 37669092 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 466 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1563 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 48845 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 34222 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1237215 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 226162 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1463377 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 314277739 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 100905928 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2095811 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 137049691 # number of memory reference insts executed
-system.cpu.iew.exec_branches 31753831 # Number of branches executed
-system.cpu.iew.exec_stores 33946670 # Number of stores executed
-system.cpu.iew.exec_rate 2.221949 # Inst execution rate
-system.cpu.iew.wb_sent 315540216 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 314707140 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 234790765 # num instructions producing a value
-system.cpu.iew.wb_consumers 320680424 # num instructions consuming a value
+system.cpu.iew.exec_refs 134999174 # number of memory reference insts executed
+system.cpu.iew.exec_branches 31825957 # Number of branches executed
+system.cpu.iew.exec_stores 34093246 # Number of stores executed
+system.cpu.iew.exec_rate 2.232903 # Inst execution rate
+system.cpu.iew.wb_sent 313326251 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 312671097 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 232527981 # num instructions producing a value
+system.cpu.iew.wb_consumers 318649991 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.205239 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.732164 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.221488 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.729729 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 71609181 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 65767670 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1277798 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 131821181 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.110378 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.644254 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1330190 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 130637438 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.129501 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.662910 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 51293193 38.91% 38.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 24103484 18.28% 57.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 17099155 12.97% 70.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 12472180 9.46% 79.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 3629365 2.75% 82.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 3499755 2.65% 85.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 3079633 2.34% 87.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1175176 0.89% 88.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 15469240 11.74% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 50443323 38.61% 38.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 24364180 18.65% 57.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 16505841 12.63% 69.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 12375620 9.47% 79.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 3710115 2.84% 82.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 3458000 2.65% 84.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 2751645 2.11% 86.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1180245 0.90% 87.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 15848469 12.13% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 131821181 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 130637438 # Number of insts commited each cycle
system.cpu.commit.count 278192519 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 122219139 # Number of memory references committed
@@ -255,49 +255,49 @@ system.cpu.commit.branches 29309710 # Nu
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
system.cpu.commit.int_insts 278186227 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 15469240 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 15848469 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 466153641 # The number of ROB reads
-system.cpu.rob.rob_writes 709355946 # The number of ROB writes
-system.cpu.timesIdled 34118 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 1152798 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 458749158 # The number of ROB reads
+system.cpu.rob.rob_writes 696922141 # The number of ROB writes
+system.cpu.timesIdled 33627 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 1126191 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 278192519 # Number of Instructions Simulated
system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated
-system.cpu.cpi 0.512986 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.512986 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.949371 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.949371 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 558552760 # number of integer regfile reads
-system.cpu.int_regfile_writes 282337727 # number of integer regfile writes
-system.cpu.fp_regfile_reads 537 # number of floating regfile reads
-system.cpu.fp_regfile_writes 378 # number of floating regfile writes
-system.cpu.misc_regfile_reads 203729290 # number of misc regfile reads
-system.cpu.icache.replacements 67 # number of replacements
-system.cpu.icache.tagsinuse 827.771382 # Cycle average of tags in use
-system.cpu.icache.total_refs 28741656 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 1030 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 27904.520388 # Average number of references to valid blocks.
+system.cpu.cpi 0.505939 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.505939 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.976523 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.976523 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 555004477 # number of integer regfile reads
+system.cpu.int_regfile_writes 279973081 # number of integer regfile writes
+system.cpu.fp_regfile_reads 378 # number of floating regfile reads
+system.cpu.fp_regfile_writes 284 # number of floating regfile writes
+system.cpu.misc_regfile_reads 201255053 # number of misc regfile reads
+system.cpu.icache.replacements 68 # number of replacements
+system.cpu.icache.tagsinuse 824.627975 # Cycle average of tags in use
+system.cpu.icache.total_refs 28269362 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 1028 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 27499.379377 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 827.771382 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.404185 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 28741656 # number of ReadReq hits
-system.cpu.icache.demand_hits 28741656 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 28741656 # number of overall hits
-system.cpu.icache.ReadReq_misses 1317 # number of ReadReq misses
-system.cpu.icache.demand_misses 1317 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 1317 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 47419000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 47419000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 47419000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 28742973 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 28742973 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 28742973 # number of overall (read+write) accesses
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@@ -307,166 +307,166 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
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+system.cpu.l2cache.overall_mshr_misses 76527 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1069946000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1069993000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1307849500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 2377795500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 2377795500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1307215500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 2377208500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 2377208500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017485 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398038 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.036826 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.036826 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.019976 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398157 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.036824 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.036824 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.483242 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31109.645576 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31069.703780 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31069.703780 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31098.263352 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31063.657271 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31063.657271 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions