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authorSteve Reinhardt <stever@gmail.com>2009-03-16 11:01:23 -0400
committerSteve Reinhardt <stever@gmail.com>2009-03-16 11:01:23 -0400
commit15f0e44060ffcf1ab6648469678cefa9081a68a1 (patch)
tree7ef3923b9ba4fc5141824e1e970ad295c5123d1f /tests/long/10.mcf/ref
parent758bfe4eb57e5b7aada4c974830532ec067a5bda (diff)
downloadgem5-15f0e44060ffcf1ab6648469678cefa9081a68a1.tar.xz
Very minor regression stats updates due top previous changeset.
Setting dirty bit on swaps added a handful of writebacks in a few of the longer-running SPARC_SE benchmarks.
Diffstat (limited to 'tests/long/10.mcf/ref')
-rwxr-xr-xtests/long/10.mcf/ref/sparc/linux/simple-timing/simout10
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt16
2 files changed, 13 insertions, 13 deletions
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
index 3aaf04828..b171def01 100755
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 24 2009 01:30:29
-M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch
-M5 started Feb 24 2009 01:31:11
-M5 executing on tater
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py long/10.mcf/sparc/linux/simple-timing
+M5 compiled Mar 16 2009 00:51:12
+M5 revision 208de84f046d 6013 default tip
+M5 started Mar 16 2009 00:51:29
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 61025e455..1e841feab 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 712663 # Simulator instruction rate (inst/s)
-host_mem_usage 336988 # Number of bytes of host memory used
-host_seconds 342.15 # Real time elapsed on the host
-host_tick_rate 1070988197 # Simulator tick rate (ticks/s)
+host_inst_rate 1212571 # Simulator instruction rate (inst/s)
+host_mem_usage 337588 # Number of bytes of host memory used
+host_seconds 201.09 # Real time elapsed on the host
+host_tick_rate 1822248337 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated
sim_seconds 0.366435 # Number of seconds simulated
@@ -80,7 +80,7 @@ system.cpu.dcache.soft_prefetch_mshr_full 0 # n
system.cpu.dcache.tagsinuse 3569.622607 # Cycle average of tags in use
system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 134379688000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 94875 # number of writebacks
+system.cpu.dcache.writebacks 94877 # number of writebacks
system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 55904.761905 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905 # average ReadReq mshr miss latency
@@ -163,8 +163,8 @@ system.cpu.l2cache.UpgradeReq_misses 48257 # nu
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1930280000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 48257 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 94875 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 94875 # number of Writeback hits
+system.cpu.l2cache.Writeback_accesses 94877 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 94877 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 51.559226 # Average number of references to valid blocks.
@@ -204,7 +204,7 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0
system.cpu.l2cache.replacements 891 # number of replacements
system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 8958.837724 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 8959.416448 # Cycle average of tags in use
system.cpu.l2cache.total_refs 802210 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 41 # number of writebacks