tests: update statistics for change caused by vsyscall support in x86

Caused by a slight change in memory layout.

3 files changed, 104 insertions, 107 deletions

diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
index 40547fe1c..c90ba3ccf 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -45,7 +45,6 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -80,7 +79,6 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -115,7 +113,6 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -152,7 +149,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
+cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
index 2a93c45ae..035c663f2 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 17 2009 20:29:57
-M5 revision 84f7bdc43a4f 6605 default qtip tip x86fsdate.patch
-M5 started Aug 17 2009 20:30:53
-M5 executing on tater
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
+M5 compiled Nov  8 2009 16:16:58
+M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff
+M5 started Nov  8 2009 16:34:05
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -28,4 +28,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 381620562000 because target called exit()
+Exiting @ tick 382091472000 because target called exit()
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
index a882827d5..b582ff405 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -1,76 +1,76 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 395133                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 355296                       # Number of bytes of host memory used
-host_seconds                                   682.55                       # Real time elapsed on the host
-host_tick_rate                              559113861                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 839358                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 328912                       # Number of bytes of host memory used
+host_seconds                                   321.31                       # Real time elapsed on the host
+host_tick_rate                             1189158712                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   269695959                       # Number of instructions simulated
-sim_seconds                                  0.381621                       # Number of seconds simulated
-sim_ticks                                381620562000                       # Number of ticks simulated
+sim_seconds                                  0.382091                       # Number of seconds simulated
+sim_ticks                                382091472000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           90779443                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 15899.099984                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12899.099984                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               88829255                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    31006234000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.021483                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              1950188                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  25155670000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.021483                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         1950188                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_avg_miss_latency 15892.729148                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12892.729148                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits               88818985                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    31157028000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.021596                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses              1960458                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  25275654000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.021596                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses         1960458                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          31439750                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000.034908                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000.034908                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              31210573                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   12833920000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.007289                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              229177                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency  12146389000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.007289                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         229177                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 56000.038268                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000.038268                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              31204566                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   13170313000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.007480                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              235184                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency  12464761000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.007480                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         235184                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  58.501856                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  58.134189                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           122219193                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 20116.021869                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 17116.021869                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               120039828                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     43840154000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.017832                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               2179365                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 20188.783508                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 17188.783508                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               120023551                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     44327341000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.017965                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               2195642                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  37302059000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.017832                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          2179365                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency  37740415000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.017965                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          2195642                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses          122219193                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 20116.021869                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 17116.021869                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 20188.783508                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 17188.783508                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              120039828                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    43840154000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.017832                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              2179365                       # number of overall misses
+system.cpu.dcache.overall_hits              120023551                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    44327341000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.017965                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              2195642                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  37302059000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.017832                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         2179365                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency  37740415000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.017965                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         2195642                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                2049944                       # number of replacements
-system.cpu.dcache.sampled_refs                2054040                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                2062715                       # number of replacements
+system.cpu.dcache.sampled_refs                2066811                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4079.426853                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                120165153                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle           127225673000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   229129                       # number of writebacks
+system.cpu.dcache.tagsinuse               4077.137530                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                120152382                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle           127457925000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   235136                       # number of writebacks
 system.cpu.icache.ReadReq_accesses          217696172                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
@@ -120,86 +120,86 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                     24                       # number of replacements
 system.cpu.icache.sampled_refs                    808                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                667.511289                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                667.480800                       # Cycle average of tags in use
 system.cpu.icache.total_refs                217695364                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses          103852                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.298502                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_accesses          106353                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.291482                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency   5400335000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   5530387000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            103852                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   4154080000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_misses            106353                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   4254120000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       103852                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses           1950996                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_mshr_misses       106353                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses           1961266                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits               1862007                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    4627428000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.045612                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               88989                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   3559560000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.045612                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          88989                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses         125325                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51990.456812                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadReq_hits               1872110                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    4636112000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.045458                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               89156                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   3566240000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.045458                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          89156                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses         128831                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51991.120150                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency   6515704000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency   6698068000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses           125325                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   5013000000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses           128831                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency   5153240000                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses       125325                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          229129                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              229129                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses       128831                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          235136                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              235136                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                 13.678118                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                 13.775269                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            2054848                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000.160754                       # average overall miss latency
+system.cpu.l2cache.demand_accesses            2067619                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000.158560                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                1862007                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    10027763000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.093847                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               192841                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                1872110                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency    10166499000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.094558                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses               195509                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   7713640000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.093847                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          192841                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   7820360000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.094558                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses          195509                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses           2054848                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000.160754                       # average overall miss latency
+system.cpu.l2cache.overall_accesses           2067619                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000.158560                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits               1862007                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   10027763000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.093847                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              192841                       # number of overall misses
+system.cpu.l2cache.overall_hits               1872110                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency   10166499000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.094558                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses              195509                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   7713640000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.093847                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         192841                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   7820360000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.094558                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses         195509                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                108886                       # number of replacements
-system.cpu.l2cache.sampled_refs                132828                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                109056                       # number of replacements
+system.cpu.l2cache.sampled_refs                132990                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             18003.313178                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1816837                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             18001.651383                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1831973                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   70892                       # number of writebacks
+system.cpu.l2cache.writebacks                   70891                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        763241124                       # number of cpu cycles simulated
+system.cpu.numCycles                        764182944                       # number of cpu cycles simulated
 system.cpu.num_insts                        269695959                       # Number of instructions executed
 system.cpu.num_refs                         122219131                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             444                       # Number of system calls