diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2011-09-13 12:58:09 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2011-09-13 12:58:09 -0400 |
| commit | 28a2236ec18e3d5a82d6f7caffbf8285aec48b38 (patch) | |
| tree | bfd2d8d78733f95b30e9f671229ce2f0f55f4d94 /tests/long/10.mcf/ref | |
| parent | 649c239ceef2d107fae253b1008c6f214f242d73 (diff) | |
| download | gem5-28a2236ec18e3d5a82d6f7caffbf8285aec48b38.tar.xz | |
O3: Update stats for new ordering fix.
Diffstat (limited to 'tests/long/10.mcf/ref')
6 files changed, 763 insertions, 763 deletions
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini index d17aac738..9bd7bf3ba 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -500,9 +500,9 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/arm/scratch/sysexplr/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout index eb9dd7dcf..67dc34515 100755 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 19:27:45 -gem5 started Aug 17 2011 21:36:25 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 12:27:58 +gem5 started Aug 20 2011 12:28:18 +gem5 executing on zizzer command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -25,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 34005216000 because target called exit() +Exiting @ tick 33049447500 because target called exit() diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt index c921edf2f..acf1a3733 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.034005 # Number of seconds simulated -sim_ticks 34005216000 # Number of ticks simulated +sim_seconds 0.033049 # Number of seconds simulated +sim_ticks 33049447500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105088 # Simulator instruction rate (inst/s) -host_tick_rate 39162055 # Simulator tick rate (ticks/s) -host_mem_usage 396412 # Number of bytes of host memory used -host_seconds 868.32 # Real time elapsed on the host -sim_insts 91249660 # Number of instructions simulated +host_inst_rate 142392 # Simulator instruction rate (inst/s) +host_tick_rate 51572715 # Simulator tick rate (ticks/s) +host_mem_usage 349636 # Number of bytes of host memory used +host_seconds 640.83 # Real time elapsed on the host +sim_insts 91249665 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,300 +51,300 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 68010433 # number of cpu cycles simulated +system.cpu.numCycles 66098896 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 28218889 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22621042 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1414269 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 25157948 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 24123842 # Number of BTB hits +system.cpu.BPredUnit.lookups 27480852 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21948199 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1405962 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 24356195 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 23358870 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 112560 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 12935 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15977103 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 135154938 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28218889 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24236402 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 33504566 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5937953 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 14110938 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 118630 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 12953 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15359689 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 131196018 # Number of instructions fetch has processed +system.cpu.fetch.Branches 27480852 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23477500 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 32529765 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5482056 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 14124387 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 185 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 15277206 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 405179 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 67980048 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.009106 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.742708 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 126 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14730221 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 368829 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 66068188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.007516 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.747063 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 34529861 50.79% 50.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6742939 9.92% 60.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5949333 8.75% 69.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5005104 7.36% 76.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2886229 4.25% 81.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1784892 2.63% 83.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1586062 2.33% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3028551 4.46% 90.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6467077 9.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 33589573 50.84% 50.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6678757 10.11% 60.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5691945 8.62% 69.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4809462 7.28% 76.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2791705 4.23% 81.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1680164 2.54% 83.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1554358 2.35% 85.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2929699 4.43% 90.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6342525 9.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 67980048 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.414920 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.987268 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 18656916 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12586941 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31365316 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1012619 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4358256 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4495895 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 29408 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 132644868 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31349 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4358256 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 20449450 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1113784 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8328298 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 30545374 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3184886 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 128012570 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 287918 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1870803 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 19 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 149350454 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 557406814 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 557400643 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6171 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429079 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 41921370 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 670708 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 672640 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 7503691 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29849221 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6023274 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1356342 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 647782 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 119728179 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 639242 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107493963 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 101688 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 28653338 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 69345788 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 84885 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 67980048 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.581258 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.754962 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 66068188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.415754 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.984844 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17938862 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 12617377 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30503596 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 985227 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4023126 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4444811 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 31491 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 129102519 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31918 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4023126 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 19654279 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1111044 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8373205 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 29732459 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3174075 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 125001528 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 255212 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1879877 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 11 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 145677643 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 544340805 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 544335582 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5223 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429087 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 38248551 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 647769 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 649953 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 7510284 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29313185 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5861466 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1226589 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 648810 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 117406606 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 634842 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 106217024 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 74725 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26332148 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 63315965 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 80484 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 66068188 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.607688 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.762772 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25411198 37.38% 37.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14672249 21.58% 58.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10091036 14.84% 73.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 8117515 11.94% 85.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4245876 6.25% 91.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2261871 3.33% 95.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2477690 3.64% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 492806 0.72% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 209807 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24256842 36.71% 36.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14242052 21.56% 58.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9853567 14.91% 73.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 8048166 12.18% 85.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4234412 6.41% 91.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2296375 3.48% 95.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2457048 3.72% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 476279 0.72% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 203447 0.31% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 67980048 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 66068188 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 55128 10.57% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.01% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 195567 37.49% 48.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 270861 51.93% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53590 10.28% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.01% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 193594 37.13% 47.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 274209 52.59% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 75624393 70.35% 70.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11037 0.01% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 142 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 216 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26489525 24.64% 95.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5368647 4.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74732015 70.36% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10984 0.01% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 117 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 183 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26127838 24.60% 94.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5345884 5.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107493963 # Type of FU issued -system.cpu.iq.rate 1.580551 # Inst issue rate -system.cpu.iq.fu_busy_cnt 521583 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.004852 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 283590457 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 149134912 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 103313429 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 788 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1184 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 356 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 108015155 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 391 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 359898 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 106217024 # Type of FU issued +system.cpu.iq.rate 1.606941 # Inst issue rate +system.cpu.iq.fu_busy_cnt 521420 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.004909 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 279097712 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144373136 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102515328 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 669 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1008 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 309 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106738111 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 333 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 366236 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7273393 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 45135 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 115664 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1276570 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6737356 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 42339 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 715 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1114761 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30487 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 30343 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4358256 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 193721 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 31151 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 120406197 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 800153 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29849221 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6023274 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 634379 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 11264 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1216 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 115664 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1297109 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 208567 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1505676 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 105540592 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 26056532 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1953371 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4023126 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 183340 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 29024 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118080266 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 812187 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29313185 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5861466 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 629989 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 9572 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1070 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 715 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1280450 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 209997 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1490447 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104523417 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25726566 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1693607 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 38776 # number of nop insts executed -system.cpu.iew.exec_refs 31276826 # number of memory reference insts executed -system.cpu.iew.exec_branches 21265794 # Number of branches executed -system.cpu.iew.exec_stores 5220294 # Number of stores executed -system.cpu.iew.exec_rate 1.551829 # Inst execution rate -system.cpu.iew.wb_sent 103749789 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 103313785 # cumulative count of insts written-back -system.cpu.iew.wb_producers 60697927 # num instructions producing a value -system.cpu.iew.wb_consumers 97489409 # num instructions consuming a value +system.cpu.iew.exec_nop 38818 # number of nop insts executed +system.cpu.iew.exec_refs 30937872 # number of memory reference insts executed +system.cpu.iew.exec_branches 21209374 # Number of branches executed +system.cpu.iew.exec_stores 5211306 # Number of stores executed +system.cpu.iew.exec_rate 1.581319 # Inst execution rate +system.cpu.iew.wb_sent 102947388 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102515637 # cumulative count of insts written-back +system.cpu.iew.wb_producers 60320212 # num instructions producing a value +system.cpu.iew.wb_consumers 97098710 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.519087 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.622610 # average fanout of values written-back +system.cpu.iew.wb_rate 1.550943 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.621226 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 91262269 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 29143453 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 554357 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1398047 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 63621793 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.434450 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.199830 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 91262274 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26817270 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 554358 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1387669 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 62045063 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.470903 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.226778 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 29598088 46.52% 46.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16825513 26.45% 72.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5309975 8.35% 81.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3950826 6.21% 87.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2115946 3.33% 90.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 645775 1.02% 91.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 466588 0.73% 92.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 200515 0.32% 92.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4508567 7.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 28329843 45.66% 45.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16548650 26.67% 72.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5280214 8.51% 80.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3902195 6.29% 87.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2034976 3.28% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 672623 1.08% 91.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 530029 0.85% 92.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 208846 0.34% 92.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4537687 7.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 63621793 # Number of insts commited each cycle -system.cpu.commit.count 91262269 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 62045063 # Number of insts commited each cycle +system.cpu.commit.count 91262274 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322531 # Number of memory references committed -system.cpu.commit.loads 22575827 # Number of loads committed +system.cpu.commit.refs 27322533 # Number of memory references committed +system.cpu.commit.loads 22575828 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18722421 # Number of branches committed +system.cpu.commit.branches 18722422 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533122 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533126 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4508567 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4537687 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 179513214 # The number of ROB reads -system.cpu.rob.rob_writes 245183550 # The number of ROB writes -system.cpu.timesIdled 1513 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30385 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 91249660 # Number of Instructions Simulated -system.cpu.committedInsts_total 91249660 # Number of Instructions Simulated -system.cpu.cpi 0.745323 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.745323 # CPI: Total CPI of All Threads -system.cpu.ipc 1.341701 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.341701 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 501285464 # number of integer regfile reads -system.cpu.int_regfile_writes 121975389 # number of integer regfile writes -system.cpu.fp_regfile_reads 172 # number of floating regfile reads -system.cpu.fp_regfile_writes 453 # number of floating regfile writes -system.cpu.misc_regfile_reads 189360420 # number of misc regfile reads -system.cpu.misc_regfile_writes 11504 # number of misc regfile writes -system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 610.965414 # Cycle average of tags in use -system.cpu.icache.total_refs 15276277 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 724 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 21099.830110 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 175581186 # The number of ROB reads +system.cpu.rob.rob_writes 240196081 # The number of ROB writes +system.cpu.timesIdled 1543 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30708 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 91249665 # Number of Instructions Simulated +system.cpu.committedInsts_total 91249665 # Number of Instructions Simulated +system.cpu.cpi 0.724374 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.724374 # CPI: Total CPI of All Threads +system.cpu.ipc 1.380502 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.380502 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 496839540 # number of integer regfile reads +system.cpu.int_regfile_writes 120902305 # number of integer regfile writes +system.cpu.fp_regfile_reads 158 # number of floating regfile reads +system.cpu.fp_regfile_writes 392 # number of floating regfile writes +system.cpu.misc_regfile_reads 184716876 # number of misc regfile reads +system.cpu.misc_regfile_writes 11506 # number of misc regfile writes +system.cpu.icache.replacements 2 # number of replacements +system.cpu.icache.tagsinuse 613.066905 # Cycle average of tags in use +system.cpu.icache.total_refs 14729300 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 718 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 20514.345404 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 610.965414 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.298323 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 15276277 # number of ReadReq hits -system.cpu.icache.demand_hits 15276277 # number of demand (read+write) hits -system.cpu.icache.overall_hits 15276277 # number of overall hits -system.cpu.icache.ReadReq_misses 929 # number of ReadReq misses -system.cpu.icache.demand_misses 929 # number of demand (read+write) misses -system.cpu.icache.overall_misses 929 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 32705500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 32705500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 32705500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 15277206 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 15277206 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 15277206 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35205.059203 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35205.059203 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35205.059203 # average overall miss latency +system.cpu.icache.occ_blocks::0 613.066905 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.299349 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 14729300 # number of ReadReq hits +system.cpu.icache.demand_hits 14729300 # number of demand (read+write) hits +system.cpu.icache.overall_hits 14729300 # number of overall hits +system.cpu.icache.ReadReq_misses 921 # number of ReadReq misses +system.cpu.icache.demand_misses 921 # number of demand (read+write) misses +system.cpu.icache.overall_misses 921 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 32465000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 32465000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 32465000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 14730221 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 14730221 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 14730221 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35249.728556 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35249.728556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35249.728556 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,139 +354,139 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 205 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 205 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 205 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 724 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 724 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 724 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 203 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 203 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 203 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 718 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 718 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 24957500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 24957500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 24957500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 24779500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 24779500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 24779500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000047 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000047 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000047 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34471.685083 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34471.685083 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34471.685083 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000049 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000049 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000049 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34511.838440 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34511.838440 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34511.838440 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943463 # number of replacements -system.cpu.dcache.tagsinuse 3549.969044 # Cycle average of tags in use -system.cpu.dcache.total_refs 29157181 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947559 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 30.770834 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12923369000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3549.969044 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.866692 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 24585710 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 4558997 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 6727 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 5747 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 29144707 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 29144707 # number of overall hits -system.cpu.dcache.ReadReq_misses 969494 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 175984 # number of WriteReq misses +system.cpu.dcache.replacements 943500 # number of replacements +system.cpu.dcache.tagsinuse 3561.430485 # Cycle average of tags in use +system.cpu.dcache.total_refs 28801207 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947596 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 30.393973 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12279149000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 3561.430485 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.869490 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 24229442 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 4559293 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 6724 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 5748 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 28788735 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 28788735 # number of overall hits +system.cpu.dcache.ReadReq_misses 990132 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 175688 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1145478 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1145478 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5401004500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4496326950 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 126500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 9897331450 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 9897331450 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 25555204 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 1165820 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1165820 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5482674500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4505328405 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 124500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 9988002905 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 9988002905 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 25219574 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 6734 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 5747 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 30290185 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 30290185 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.037937 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.037167 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_accesses 6731 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 5748 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 29954555 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 29954555 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.039260 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.037104 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.001040 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.037817 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.037817 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 5570.951961 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 25549.634910 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 18071.428571 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 8640.350535 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 8640.350535 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23178020 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.038920 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.038920 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 5537.316742 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 25643.916517 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 17785.714286 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 8567.362805 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 8567.362805 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23285977 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8098 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8139 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2862.190664 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2861.036614 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 942900 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 67979 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 129940 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 942954 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 87074 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 131149 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 197919 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 197919 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 901515 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 46044 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 947559 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 947559 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 218223 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 218223 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 903058 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 44539 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 947597 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 947597 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2251061000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1080314076 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3331375076 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3331375076 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2256691000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1081795530 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3338486530 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3338486530 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.035277 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009724 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.031283 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.031283 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2496.975647 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23462.646078 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3515.744219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3515.744219 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.035808 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.031634 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.031634 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2498.943589 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24288.725162 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3523.107956 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3523.107956 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 745 # number of replacements -system.cpu.l2cache.tagsinuse 9143.143652 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1595891 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15573 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 102.478071 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 742 # number of replacements +system.cpu.l2cache.tagsinuse 9256.207068 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1596737 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15558 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 102.631251 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 398.185089 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 8744.958563 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.012152 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.266875 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 901164 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 942900 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 31521 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 932685 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 932685 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1058 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::0 391.956879 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 8864.250189 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.011962 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.270515 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 901452 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 942954 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 31278 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 932730 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 932730 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1045 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 14540 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 15598 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 15598 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 36283000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 498900000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 535183000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 535183000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 902222 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 942900 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 46061 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 948283 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 948283 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.001173 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.315668 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.016449 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.016449 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34293.950851 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34312.242091 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34311.001410 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34311.001410 # average overall miss latency +system.cpu.l2cache.demand_misses 15585 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 15585 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 35800500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 498909000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 534709500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 534709500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 902497 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 942954 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 45818 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 948315 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 948315 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.001158 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.317343 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.016434 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.016434 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34258.851675 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34312.861073 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34309.239654 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34309.239654 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -499,24 +499,24 @@ system.cpu.l2cache.writebacks 32 # nu system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1048 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 1035 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 14540 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 15588 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 15588 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 15575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 15575 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 32620500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 451750500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 484371000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 484371000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 32188500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 451730000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 483918500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 483918500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001162 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.315668 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.016438 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.016438 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31126.431298 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.497937 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31073.325635 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31073.325635 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001147 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317343 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.016424 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.016424 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31100 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31068.088033 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31070.208668 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31070.208668 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini index aaea60ae0..df2fb6f73 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -500,9 +500,9 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/x86/linux/mcf +executable=/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/arm/scratch/sysexplr/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout index 796b5db5e..d1aeffbca 100755 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 17:25:41 -gem5 started Aug 17 2011 17:30:37 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 13:24:14 +gem5 started Aug 20 2011 13:24:28 +gem5 executing on zizzer command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -25,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 71354418000 because target called exit() +Exiting @ tick 70374234500 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt index 542fef85a..f17fe7434 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.071354 # Number of seconds simulated -sim_ticks 71354418000 # Number of ticks simulated +sim_seconds 0.070374 # Number of seconds simulated +sim_ticks 70374234500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121216 # Simulator instruction rate (inst/s) -host_tick_rate 31091054 # Simulator tick rate (ticks/s) -host_mem_usage 393776 # Number of bytes of host memory used -host_seconds 2295.01 # Real time elapsed on the host +host_inst_rate 169063 # Simulator instruction rate (inst/s) +host_tick_rate 42767879 # Simulator tick rate (ticks/s) +host_mem_usage 346452 # Number of bytes of host memory used +host_seconds 1645.49 # Real time elapsed on the host sim_insts 278192519 # Number of instructions simulated system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 142708837 # number of cpu cycles simulated +system.cpu.numCycles 140748470 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 38713050 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 38713050 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1277784 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 34149959 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 33632947 # Number of BTB hits +system.cpu.BPredUnit.lookups 37906853 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 37906853 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1330176 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 33468761 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 32955372 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29563972 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 207959070 # Number of instructions fetch has processed -system.cpu.fetch.Branches 38713050 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33632947 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 64671203 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11251281 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37585887 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 29094074 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 203757407 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37906853 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32955372 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 63225813 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 10352620 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 38317432 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 97 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 28742973 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 228078 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 141556039 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.590408 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.296325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 28270666 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 203655 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 139622279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.575042 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.293353 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 79448784 56.13% 56.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3733414 2.64% 58.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2922001 2.06% 60.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4489594 3.17% 64.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6936058 4.90% 68.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5469177 3.86% 72.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 7685058 5.43% 78.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4534397 3.20% 81.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 26337556 18.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 78878326 56.49% 56.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3468234 2.48% 58.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2811542 2.01% 60.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4524513 3.24% 64.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6755323 4.84% 69.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5317016 3.81% 72.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 7687744 5.51% 78.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4301095 3.08% 81.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25878486 18.53% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 141556039 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.271273 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.457226 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 42383946 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 28100231 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 53949523 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7387481 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9734858 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 362029152 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 9734858 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 49345988 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4251907 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6895 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 54198746 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24017645 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 357077595 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 112284 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20035490 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 320906324 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 879462898 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 879458894 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4004 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 139622279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.269323 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.447670 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 41959628 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 28656621 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 52572729 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7448460 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8984841 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 355072137 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 8984841 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 48879402 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4457870 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6893 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 52910993 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24382280 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 350563031 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 104227 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20384891 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 314779048 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 862154595 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 862151489 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3106 # Number of floating rename lookups system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 72562132 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 66434856 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 479 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 472 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 56213524 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 115636696 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38304742 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 48747327 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8476101 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 349796606 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 465 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 319480009 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 127874 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 71460780 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 105775967 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 141556039 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.256915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.760467 # Number of insts issued each cycle +system.cpu.rename.skidInsts 56483579 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 112824537 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37669092 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 48262856 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8162457 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343955075 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 466 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 316373550 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 98329 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 65563048 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 93813941 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 139622279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.265925 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.753143 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 32928700 23.26% 23.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 18859354 13.32% 36.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25409770 17.95% 54.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 30153045 21.30% 75.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18699176 13.21% 89.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 10380312 7.33% 96.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3284045 2.32% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1793650 1.27% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 47987 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 31939796 22.88% 22.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 18447556 13.21% 36.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25584563 18.32% 54.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 29944678 21.45% 75.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18447649 13.21% 89.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 10291416 7.37% 96.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3138355 2.25% 98.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1781100 1.28% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 47166 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 141556039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 139622279 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 25871 1.36% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1792047 94.50% 95.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78518 4.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 26426 1.39% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1802884 94.84% 96.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 71697 3.77% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 181286722 56.74% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 231 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103851207 32.51% 89.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34325138 10.74% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 180370396 57.01% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 163 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101485830 32.08% 89.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34500450 10.90% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 319480009 # Type of FU issued -system.cpu.iq.rate 2.238684 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1896436 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005936 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 782539275 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 421630860 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 314706696 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1092 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2558 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 444 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 321359193 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 541 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 45621060 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 316373550 # Type of FU issued +system.cpu.iq.rate 2.247794 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1901007 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006009 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 774367858 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 409550255 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 312670753 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 857 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1937 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 344 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 318257421 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 425 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 45906074 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 24857308 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 124101 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 396603 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6864991 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 22045149 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 125133 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34222 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6229341 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2744 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 15359 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2799 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 15405 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9734858 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 919734 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 96297 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 349797071 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 26061 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 115636696 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38304742 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6174 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 48786 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 396603 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1201294 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 194628 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1395922 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 317091801 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103103021 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2388208 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8984841 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 901233 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 88686 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343955541 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 25713 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 112824537 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 37669092 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 466 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1563 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 48845 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34222 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1237215 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 226162 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1463377 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 314277739 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100905928 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2095811 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 137049691 # number of memory reference insts executed -system.cpu.iew.exec_branches 31753831 # Number of branches executed -system.cpu.iew.exec_stores 33946670 # Number of stores executed -system.cpu.iew.exec_rate 2.221949 # Inst execution rate -system.cpu.iew.wb_sent 315540216 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 314707140 # cumulative count of insts written-back -system.cpu.iew.wb_producers 234790765 # num instructions producing a value -system.cpu.iew.wb_consumers 320680424 # num instructions consuming a value +system.cpu.iew.exec_refs 134999174 # number of memory reference insts executed +system.cpu.iew.exec_branches 31825957 # Number of branches executed +system.cpu.iew.exec_stores 34093246 # Number of stores executed +system.cpu.iew.exec_rate 2.232903 # Inst execution rate +system.cpu.iew.wb_sent 313326251 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 312671097 # cumulative count of insts written-back +system.cpu.iew.wb_producers 232527981 # num instructions producing a value +system.cpu.iew.wb_consumers 318649991 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.205239 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.732164 # average fanout of values written-back +system.cpu.iew.wb_rate 2.221488 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.729729 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 71609181 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 65767670 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1277798 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131821181 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.110378 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.644254 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1330190 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130637438 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.129501 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.662910 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 51293193 38.91% 38.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 24103484 18.28% 57.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 17099155 12.97% 70.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12472180 9.46% 79.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3629365 2.75% 82.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3499755 2.65% 85.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3079633 2.34% 87.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1175176 0.89% 88.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15469240 11.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 50443323 38.61% 38.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 24364180 18.65% 57.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 16505841 12.63% 69.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12375620 9.47% 79.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3710115 2.84% 82.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3458000 2.65% 84.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2751645 2.11% 86.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1180245 0.90% 87.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15848469 12.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131821181 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 130637438 # Number of insts commited each cycle system.cpu.commit.count 278192519 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 122219139 # Number of memory references committed @@ -255,49 +255,49 @@ system.cpu.commit.branches 29309710 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186227 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15469240 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15848469 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 466153641 # The number of ROB reads -system.cpu.rob.rob_writes 709355946 # The number of ROB writes -system.cpu.timesIdled 34118 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1152798 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 458749158 # The number of ROB reads +system.cpu.rob.rob_writes 696922141 # The number of ROB writes +system.cpu.timesIdled 33627 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1126191 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 278192519 # Number of Instructions Simulated system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated -system.cpu.cpi 0.512986 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.512986 # CPI: Total CPI of All Threads -system.cpu.ipc 1.949371 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.949371 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 558552760 # number of integer regfile reads -system.cpu.int_regfile_writes 282337727 # number of integer regfile writes -system.cpu.fp_regfile_reads 537 # number of floating regfile reads -system.cpu.fp_regfile_writes 378 # number of floating regfile writes -system.cpu.misc_regfile_reads 203729290 # number of misc regfile reads -system.cpu.icache.replacements 67 # number of replacements -system.cpu.icache.tagsinuse 827.771382 # Cycle average of tags in use -system.cpu.icache.total_refs 28741656 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1030 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 27904.520388 # Average number of references to valid blocks. +system.cpu.cpi 0.505939 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.505939 # CPI: Total CPI of All Threads +system.cpu.ipc 1.976523 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.976523 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 555004477 # number of integer regfile reads +system.cpu.int_regfile_writes 279973081 # number of integer regfile writes +system.cpu.fp_regfile_reads 378 # number of floating regfile reads +system.cpu.fp_regfile_writes 284 # number of floating regfile writes +system.cpu.misc_regfile_reads 201255053 # number of misc regfile reads +system.cpu.icache.replacements 68 # number of replacements +system.cpu.icache.tagsinuse 824.627975 # Cycle average of tags in use +system.cpu.icache.total_refs 28269362 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1028 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 27499.379377 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 827.771382 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.404185 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 28741656 # number of ReadReq hits -system.cpu.icache.demand_hits 28741656 # number of demand (read+write) hits -system.cpu.icache.overall_hits 28741656 # number of overall hits -system.cpu.icache.ReadReq_misses 1317 # number of ReadReq misses -system.cpu.icache.demand_misses 1317 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1317 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 47419000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 47419000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 47419000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 28742973 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 28742973 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 28742973 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 824.627975 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.402650 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 28269362 # number of ReadReq hits +system.cpu.icache.demand_hits 28269362 # number of demand (read+write) hits +system.cpu.icache.overall_hits 28269362 # number of overall hits +system.cpu.icache.ReadReq_misses 1304 # number of ReadReq misses +system.cpu.icache.demand_misses 1304 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1304 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 47096500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 47096500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 47096500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 28270666 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 28270666 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 28270666 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36005.315110 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36005.315110 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36005.315110 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 36116.947853 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36116.947853 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36116.947853 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -307,166 +307,166 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 286 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 286 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 286 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1031 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1031 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1031 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 275 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 275 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 275 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1029 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1029 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1029 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 36294500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 36294500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 36294500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 36215000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 36215000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 36215000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35203.200776 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35203.200776 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35203.200776 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35194.363460 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35194.363460 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35194.363460 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2073043 # number of replacements -system.cpu.dcache.tagsinuse 4075.910712 # Cycle average of tags in use -system.cpu.dcache.total_refs 86335085 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2077139 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 41.564423 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 24475195000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4075.910712 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995095 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 55138633 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 31196443 # number of WriteReq hits -system.cpu.dcache.demand_hits 86335076 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 86335076 # number of overall hits -system.cpu.dcache.ReadReq_misses 2261245 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 243308 # number of WriteReq misses -system.cpu.dcache.demand_misses 2504553 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2504553 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 14586168500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4411412645 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 18997581145 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 18997581145 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 57399878 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2073072 # number of replacements +system.cpu.dcache.tagsinuse 4076.002534 # Cycle average of tags in use +system.cpu.dcache.total_refs 83850634 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2077168 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 40.367767 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 23897616000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4076.002534 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995118 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 52653882 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 31196743 # number of WriteReq hits +system.cpu.dcache.demand_hits 83850625 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 83850625 # number of overall hits +system.cpu.dcache.ReadReq_misses 2263157 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 243008 # number of WriteReq misses +system.cpu.dcache.demand_misses 2506165 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2506165 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 14623728000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4401886592 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 19025614592 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 19025614592 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 54917039 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 88839629 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 88839629 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.039395 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.007739 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.028192 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.028192 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 6450.503373 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 18130.980671 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 7585.218259 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 7585.218259 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 284500 # number of cycles access was blocked +system.cpu.dcache.demand_accesses 86356790 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 86356790 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.041210 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.007729 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.029021 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.029021 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 6461.649810 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 18114.163287 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 7591.525136 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 7591.525136 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 296000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 87 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 93 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3270.114943 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3182.795699 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1447109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 289614 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 137796 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 427410 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 427410 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1971631 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 105512 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2077143 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2077143 # number of overall MSHR misses +system.cpu.dcache.writebacks 1447092 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 291450 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 137543 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 428993 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 428993 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1971707 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 105465 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2077172 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2077172 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5604635500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1879175645 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7483811145 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7483811145 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 5599733000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1876757592 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7476490592 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7476490592 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.034349 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003356 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.023381 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.023381 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2842.639165 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17810.065632 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3602.934966 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3602.934966 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.035903 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.024053 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.024053 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2840.043171 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17795.075068 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3599.360377 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3599.360377 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 49075 # number of replacements -system.cpu.l2cache.tagsinuse 18765.136445 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3317892 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 77084 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 43.042551 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 49070 # number of replacements +system.cpu.l2cache.tagsinuse 18849.812777 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3318008 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 77081 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 43.045731 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 6711.152997 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 12053.983448 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.204808 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.367858 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1938063 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1447109 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 63578 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2001641 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2001641 # number of overall hits -system.cpu.l2cache.ReadReq_misses 34491 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::0 6745.826593 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 12103.986183 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.205866 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.369384 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1938133 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1447092 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 63539 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 2001672 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2001672 # number of overall hits +system.cpu.l2cache.ReadReq_misses 34492 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 42040 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 76531 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 76531 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1179737500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1440022500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 2619760000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 2619760000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1972554 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1447109 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses 42035 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 76527 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 76527 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1179607000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1438839000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 2618446000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 2618446000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1972625 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1447092 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 105618 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2078172 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2078172 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses 105574 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2078199 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2078199 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate 0.017485 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.398038 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.036826 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.036826 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34204.212693 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34253.627498 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34231.357228 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34231.357228 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate 0.398157 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.036824 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.036824 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34199.437551 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34229.546806 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34215.976061 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34215.976061 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 39000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2884.615385 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2785.714286 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 29187 # number of writebacks +system.cpu.l2cache.writebacks 29193 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 34491 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 34492 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 42040 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 76531 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 76531 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 42035 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 76527 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 76527 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1069946000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1069993000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1307849500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2377795500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2377795500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1307215500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2377208500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2377208500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017485 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398038 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.036826 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.036826 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.019976 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398157 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.036824 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.036824 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.483242 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31109.645576 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31069.703780 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31069.703780 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31098.263352 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31063.657271 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31063.657271 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |