SE/FS: Make both SE and FS tests available all the time.

--HG--
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm
rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simout => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/test.py => tests/long/se/00.gzip/test.py
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simout => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simout => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simout => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/test.py => tests/long/se/10.mcf/test.py
rename : tests/long/20.parser/ref/alpha/tru64/NOTE => tests/long/se/20.parser/ref/alpha/tru64/NOTE
rename : tests/long/20.parser/ref/arm/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simerr => tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simout => tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
rename : tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simerr => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simout => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-timing/simerr => tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-timing/simout => tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
rename : tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/x86/linux/o3-timing/simerr => tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
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rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
rename : tests/quick/10.linux-boot/test.py => tests/quick/fs/10.linux-boot/test.py
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
rename : tests/quick/80.netperf-stream/test.py => tests/quick/fs/80.netperf-stream/test.py
rename : tests/quick/00.hello.mp/test.py => tests/quick/se/00.hello.mp/test.py
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr
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rename : tests/quick/01.hello-2T-smt/test.py => tests/quick/se/01.hello-2T-smt/test.py
rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
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rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
rename : tests/quick/02.insttest/test.py => tests/quick/se/02.insttest/test.py
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/config.ini
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rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
rename : tests/quick/20.eio-short/test.py => tests/quick/se/20.eio-short/test.py
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
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rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
rename : tests/quick/50.memtest/test.py => tests/quick/se/50.memtest/test.py
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py

43 files changed, 0 insertions, 12182 deletions

diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm b/tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm
deleted file mode 100644
index 9ac19076f..000000000
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm
+++ /dev/null
@@ -1,4 +0,0 @@
-P6
-15 15
-255
-


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\ No newline at end of file
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
deleted file mode 100644
index bec9490f3..000000000
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ /dev/null
@@ -1,535 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-memories=system.physmem
-num_work_ids=16
-physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[0]
-
-[system.cpu]
-type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
-BTBEntries=4096
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-clock=500
-commitToDecodeDelay=1
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-cpu_id=0
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-decodeWidth=8
-defer_registration=false
-dispatchWidth=8
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-fetchToDecodeDelay=1
-fetchTrapLatency=1
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-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
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-iewToCommitDelay=1
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-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
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-phase=0
-predType=tournament
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
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-renameToROBDelay=1
-renameWidth=8
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
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-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-squashWidth=8
-store_set_clear_period=250000
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbDepth=1
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=262144
-subblock_size=0
-tgts_per_mshr=20
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.dtb]
-type=ArmTLB
-size=64
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
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-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
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-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
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-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
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-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
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-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
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-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
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-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
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-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList
-count=0
-opList=system.cpu.fuPool.FUList4.opList
-
-[system.cpu.fuPool.FUList4.opList]
-type=OpDesc
-issueLat=1
-opClass=MemRead
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-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
-
-[system.cpu.fuPool.FUList5.opList00]
-type=OpDesc
-issueLat=1
-opClass=SimdAdd
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-
-[system.cpu.fuPool.FUList5.opList01]
-type=OpDesc
-issueLat=1
-opClass=SimdAddAcc
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-
-[system.cpu.fuPool.FUList5.opList02]
-type=OpDesc
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-opClass=SimdAlu
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-
-[system.cpu.fuPool.FUList5.opList03]
-type=OpDesc
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-opClass=SimdCmp
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList04]
-type=OpDesc
-issueLat=1
-opClass=SimdCvt
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList05]
-type=OpDesc
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-
-[system.cpu.fuPool.FUList5.opList06]
-type=OpDesc
-issueLat=1
-opClass=SimdMult
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList07]
-type=OpDesc
-issueLat=1
-opClass=SimdMultAcc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList08]
-type=OpDesc
-issueLat=1
-opClass=SimdShift
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-
-[system.cpu.fuPool.FUList5.opList09]
-type=OpDesc
-issueLat=1
-opClass=SimdShiftAcc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList10]
-type=OpDesc
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-
-[system.cpu.fuPool.FUList5.opList11]
-type=OpDesc
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-opClass=SimdFloatAdd
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-
-[system.cpu.fuPool.FUList5.opList12]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatAlu
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList13]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatCmp
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList14]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatCvt
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList15]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatDiv
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-
-[system.cpu.fuPool.FUList5.opList16]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatMisc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList17]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatMult
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-
-[system.cpu.fuPool.FUList5.opList18]
-type=OpDesc
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-opClass=SimdFloatMultAcc
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-
-[system.cpu.fuPool.FUList5.opList19]
-type=OpDesc
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-opClass=SimdFloatSqrt
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
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-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
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-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
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-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
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-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList7.opList1]
-type=OpDesc
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-
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-opList=system.cpu.fuPool.FUList8.opList
-
-[system.cpu.fuPool.FUList8.opList]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=131072
-subblock_size=0
-tgts_per_mshr=20
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.itb]
-type=ArmTLB
-size=64
-
-[system.cpu.l2cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=2097152
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
-
-[system.cpu.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=mcf mcf.in
-cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
-gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=55300000000
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:268435455
-zero=false
-port=system.membus.port[1]
-
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out b/tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out
deleted file mode 100644
index 095132477..000000000
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out
+++ /dev/null
@@ -1,999 +0,0 @@
-()
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-()
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-()
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-()
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-()
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-()
-114
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-()
-113
-***
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-()
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-***
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-()
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-()
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-()
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-()
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-***
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-()
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-()
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-***
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-()
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-()
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-***
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-()
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-()
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-()
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-()
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-()
-69
-()
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-()
-66
-()
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-()
-62
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-256
-()
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-93
-()
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-()
-58
-()
-57
-***
-183
-()
-55
-()
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-()
-51
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-()
-50
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-()
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-()
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-***
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-()
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-()
-46
-***
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-()
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-***
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-()
-44
-()
-43
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-88
-()
-42
-***
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-()
-41
-***
-91
-()
-40
-***
-96
-()
-38
-***
-100
-()
-37
-***
-149
-()
-36
-***
-74
-()
-35
-***
-258
-()
-34
-***
-151
-()
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-85
-()
-32
-()
-31
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-94
-()
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-***
-97
-()
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-90
-()
-28
-***
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-()
-27
-***
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-()
-26
-***
-72
-***
-247
-()
-25
-***
-86
-()
-24
-***
-82
-()
-23
-***
-87
-***
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-()
-22
-***
-76
-***
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-()
-21
-***
-84
-()
-20
-***
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-()
-19
-***
-73
-()
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-()
-17
-***
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-()
-16
-***
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-()
-15
-***
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-()
-14
-***
-75
-()
-13
-***
-322
-()
-12
-***
-77
-()
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-***
-283
-()
-10
-***
-79
-()
-9
-***
-145
-***
-150
-()
-8
-***
-67
-()
-7
-***
-60
-***
-231
-()
-6
-***
-56
-***
-234
-()
-5
-***
-164
-***
-202
-()
-4
-***
-53
-()
-3
-***
-130
-***
-185
-***
-200
-()
-2
-***
-205
-()
-1
-***
-39
-***
-95
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simerr b/tests/long/10.mcf/ref/arm/linux/o3-timing/simerr
deleted file mode 100755
index e45cd058f..000000000
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simerr
+++ /dev/null
@@ -1,2 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
deleted file mode 100755
index db74d3d24..000000000
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
+++ /dev/null
@@ -1,26 +0,0 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 08:43:41
-gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-
-MCF SPEC version 1.6.I
-by  Andreas Loebel
-Copyright (c) 1998,1999   ZIB Berlin
-All Rights Reserved.
-
-nodes                      : 500
-active arcs                : 1905
-simplex iterations         : 1502
-flow value                 : 4990014995
-new implicit arcs          : 23867
-active arcs                : 25772
-simplex iterations         : 2663
-flow value                 : 3080014995
-checksum                   : 68389
-optimal
-Exiting @ tick 33080569000 because target called exit()
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
deleted file mode 100644
index 190781128..000000000
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ /dev/null
@@ -1,536 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.033081                       # Number of seconds simulated
-sim_ticks                                 33080569000                       # Number of ticks simulated
-final_tick                                33080569000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 140676                       # Simulator instruction rate (inst/s)
-host_tick_rate                               50998874                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 353196                       # Number of bytes of host memory used
-host_seconds                                   648.65                       # Real time elapsed on the host
-sim_insts                                    91249885                       # Number of instructions simulated
-system.physmem.bytes_read                      997440                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  44864                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     2048                       # Number of bytes written to this memory
-system.physmem.num_reads                        15585                       # Number of read requests responded to by this memory
-system.physmem.num_writes                          32                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       30151839                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                   1356204                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                         61909                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      30213749                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                         66161139                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 27503856                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           21975755                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            1408867                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              24498145                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 23511296                       # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                   109835                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect               10070                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           15373276                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      131330352                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    27503856                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           23621131                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      32575580                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 5466802                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               14146451                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles            14                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  14744728                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                369535                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           66131343                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.004854                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.741973                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 33609066     50.82%     50.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  6636464     10.04%     60.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  5762437      8.71%     69.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  4857984      7.35%     76.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2814891      4.26%     81.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1640731      2.48%     83.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1559267      2.36%     86.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  2974436      4.50%     90.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  6276067      9.49%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             66131343                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.415710                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.985007                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 17946396                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              12652276                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  30529024                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                996648                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4006999                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              4433202                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 29411                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              129091755                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 32642                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                4006999                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 19654600                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 1107804                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles        8424491                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  29777332                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               3160117                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              124853414                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    19                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 254616                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               1879605                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents                6                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           145685583                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             543523067                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        543516086                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              6981                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             107429439                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 38256144                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             662187                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         664355                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   7619533                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             29336350                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             5741000                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1194254                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           692979                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  117270516                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded              648807                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 106162042                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             30561                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        26211084                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     62748223                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          93963                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      66131343                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.605321                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.761707                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            24322507     36.78%     36.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            14238727     21.53%     58.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             9857796     14.91%     73.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             8080873     12.22%     85.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4216462      6.38%     91.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2267133      3.43%     95.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2478028      3.75%     98.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              463113      0.70%     99.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              206704      0.31%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        66131343                       # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   52363     10.31%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     27      0.01%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 192834     37.95%     48.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                262907     51.74%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              74696384     70.36%     70.36% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                11141      0.01%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               1      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt             159      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc            260      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26155378     24.64%     95.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             5298717      4.99%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              106162042                       # Type of FU issued
-system.cpu.iq.rate                           1.604598                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                      508131                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.004786                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          278993219                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         144129610                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    102521129                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 900                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               1354                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          412                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              106669721                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     452                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           366276                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6760478                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        42465                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation          731                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       994251                       # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads            2                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         30282                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4006999                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  182542                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 28701                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           117958129                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            810273                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              29336350                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              5741000                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             643936                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   9429                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  1050                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents            731                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1288873                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       210071                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1498944                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             104530426                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25743276                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1631616                       # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         38806                       # number of nop insts executed
-system.cpu.iew.exec_refs                     30946109                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 21214083                       # Number of branches executed
-system.cpu.iew.exec_stores                    5202833                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.579937                       # Inst execution rate
-system.cpu.iew.wb_sent                      102941811                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     102521541                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  60312663                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  96996327                       # num instructions consuming a value
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.549573                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.621804                       # average fanout of values written-back
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts       91262494                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        26696986                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          554844                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1392644                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     62124345                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.469029                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.224973                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     28387912     45.70%     45.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     16565318     26.66%     72.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      5280655      8.50%     80.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      3908699      6.29%     87.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2045216      3.29%     90.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       660602      1.06%     91.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       536847      0.86%     92.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       207955      0.33%     92.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      4531141      7.29%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     62124345                       # Number of insts commited each cycle
-system.cpu.commit.count                      91262494                       # Number of instructions committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       27322621                       # Number of memory references committed
-system.cpu.commit.loads                      22575872                       # Number of loads committed
-system.cpu.commit.membars                        3888                       # Number of memory barriers committed
-system.cpu.commit.branches                   18722466                       # Number of branches committed
-system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  72533302                       # Number of committed integer instructions.
-system.cpu.commit.function_calls                56148                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               4531141                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    175546950                       # The number of ROB reads
-system.cpu.rob.rob_writes                   239939834                       # The number of ROB writes
-system.cpu.timesIdled                            1543                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           29796                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                    91249885                       # Number of Instructions Simulated
-system.cpu.committedInsts_total              91249885                       # Number of Instructions Simulated
-system.cpu.cpi                               0.725054                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.725054                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.379207                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.379207                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                496902731                       # number of integer regfile reads
-system.cpu.int_regfile_writes               120936097                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       197                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      534                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               184886725                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                  11594                       # number of misc regfile writes
-system.cpu.icache.replacements                      2                       # number of replacements
-system.cpu.icache.tagsinuse                611.587678                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 14743812                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    722                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               20420.792244                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            611.587678                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.298627                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               14743812                       # number of ReadReq hits
-system.cpu.icache.demand_hits                14743812                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               14743812                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  916                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   916                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  916                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       32376000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        32376000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       32376000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           14744728                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            14744728                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           14744728                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000062                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000062                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000062                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 35344.978166                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 35344.978166                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 35344.978166                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               194                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                194                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               194                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             722                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              722                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             722                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     24887000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     24887000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     24887000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000049                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000049                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000049                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34469.529086                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34469.529086                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34469.529086                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 943456                       # number of replacements
-system.cpu.dcache.tagsinuse               3558.808717                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 28819274                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 947552                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  30.414451                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            12353041000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           3558.808717                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.868850                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               24247443                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits               4559242                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits             6797                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits              5792                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits                28806685                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               28806685                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               989267                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              175739                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses              7                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses               1165006                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              1165006                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     5475542500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    4498706928                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency       124500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency      9974249428                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency     9974249428                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           25236710                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses           4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses         6804                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses          5792                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            29971691                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           29971691                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.039200                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.037115                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.001029                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.038870                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.038870                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency  5534.949109                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 25598.796670                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 17785.714286                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency  8561.543398                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency  8561.543398                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     23239503                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              8123                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  2860.950757                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   942907                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits             86240                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits           131213                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits            7                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits             217453                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits            217453                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          903027                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses          44526                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           947553                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          947553                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   2253075000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   1081062556                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   3334137556                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   3334137556                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.035782                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.009404                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.031615                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.031615                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2495.025066                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24279.354894                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  3518.681864                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  3518.681864                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                   744                       # number of replacements
-system.cpu.l2cache.tagsinuse              9229.669539                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1596774                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 15569                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                102.561115                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           392.792284                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          8836.877255                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.011987                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.269680                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                901413                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              942907                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               31267                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 932680                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                932680                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                1057                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             14538                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                15595                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               15595                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      36209000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency    498763000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      534972000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     534972000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            902470                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          942907                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses           45805                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             948275                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            948275                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.001171                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.317389                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.016446                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.016446                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34256.385998                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34307.538864                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34304.071818                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34304.071818                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                      32                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits               10                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits                10                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits               10                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           1047                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        14538                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           15585                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          15585                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     32560500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    451777500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    484338000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    484338000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.001160                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.317389                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.016435                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.016435                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31098.853868                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31075.629385                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31077.189605                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31077.189605                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm b/tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
deleted file mode 100644
index 9ac19076f..000000000
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
+++ /dev/null
@@ -1,4 +0,0 @@
-P6
-15 15
-255
-


			   !!!   !!!$$$&&&'''&&&%%%


!!!%%%(((******)))(((!!!###'''***+++,,,+++)))"""###''')))++++++***)))!!!!!!%%%((()))))))))'''   """%%%&&&'''&&&%%%%%%      !!!"""#########"""(((---222666&&&...///===;;;999555111,,,((($$$DDDKKKRRRXXXBBB†††‘‘‘jjjWWWZZZUUUNNNGGG???888[[[dddkkkrrr]]]CCC===eeeaaarrrkkkddd[[[SSSKKKiiipppvvvvvvEEEggg{{{uuunnnfff^^^VVVmmmsssxxx|||oooEEEDDD]]]vvvzzzuuuooohhhaaaZZZjjjooossswwwyyyzzzzzzyyywwwtttoookkkeee```ZZZeeeiiilllnnnpppppppppooonnnkkkhhhddd```\\\WWW
\ No newline at end of file
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
deleted file mode 100644
index 67a5d19a5..000000000
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ /dev/null
@@ -1,102 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-memories=system.physmem
-num_work_ids=16
-physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[0]
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb itb tracer workload
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
-
-[system.cpu.dtb]
-type=ArmTLB
-size=64
-
-[system.cpu.itb]
-type=ArmTLB
-size=64
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=mcf mcf.in
-cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
-gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=55300000000
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:268435455
-zero=false
-port=system.membus.port[1]
-
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out b/tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out
deleted file mode 100644
index 095132477..000000000
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out
+++ /dev/null
@@ -1,999 +0,0 @@
-()
-500
-()
-499
-()
-498
-()
-496
-()
-495
-()
-494
-()
-493
-()
-492
-()
-491
-()
-490
-()
-489
-()
-488
-()
-487
-()
-486
-()
-484
-()
-482
-()
-481
-()
-480
-()
-479
-()
-478
-()
-477
-()
-476
-()
-475
-()
-474
-()
-473
-()
-472
-()
-471
-()
-469
-()
-468
-()
-467
-()
-466
-()
-465
-()
-464
-()
-463
-()
-462
-()
-461
-()
-460
-()
-459
-()
-458
-()
-457
-()
-455
-()
-454
-()
-452
-()
-451
-()
-450
-()
-449
-()
-448
-()
-446
-()
-445
-()
-444
-()
-443
-()
-442
-()
-440
-()
-439
-()
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-432
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-()
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-420
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-419
-()
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-414
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-407
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-402
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-398
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-396
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-390
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-389
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-388
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-()
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-()
-385
-()
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-()
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-()
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-381
-()
-380
-()
-379
-()
-377
-()
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-()
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-()
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-()
-372
-()
-371
-()
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-()
-369
-()
-368
-()
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-()
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-()
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-()
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-()
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-()
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-339
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-()
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-237
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-()
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-()
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-()
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-()
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-***
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-()
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-327
-()
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-()
-199
-***
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-()
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-()
-197
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-220
-()
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-429
-()
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-193
-***
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-()
-191
-***
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-()
-190
-***
-263
-()
-189
-215
-***
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-()
-188
-***
-266
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-()
-182
-***
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-()
-181
-***
-351
-()
-180
-***
-441
-()
-179
-***
-453
-()
-178
-***
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-()
-177
-***
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-()
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-422
-()
-175
-***
-225
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-()
-174
-***
-269
-()
-173
-***
-214
-()
-172
-***
-186
-()
-171
-***
-447
-()
-170
-***
-270
-***
-306
-()
-169
-***
-336
-()
-168
-***
-285
-()
-165
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-249
-()
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-***
-154
-()
-143
-***
-334
-()
-142
-***
-216
-***
-257
-()
-141
-***
-167
-***
-251
-()
-140
-***
-162
-***
-293
-()
-139
-***
-158
-()
-137
-***
-166
-***
-201
-()
-136
-***
-160
-()
-134
-***
-221
-()
-132
-***
-213
-()
-131
-***
-187
-()
-129
-***
-235
-()
-128
-***
-153
-()
-127
-***
-156
-()
-126
-***
-159
-***
-218
-()
-125
-***
-155
-()
-124
-***
-157
-()
-123
-***
-152
-()
-116
-***
-135
-***
-163
-()
-115
-***
-133
-***
-204
-***
-248
-()
-114
-***
-192
-***
-212
-()
-113
-***
-268
-()
-112
-***
-367
-()
-111
-***
-272
-()
-110
-***
-434
-()
-109
-***
-323
-()
-108
-***
-281
-()
-107
-***
-144
-***
-148
-()
-106
-***
-275
-()
-105
-***
-196
-***
-254
-()
-104
-***
-138
-***
-161
-()
-103
-***
-310
-()
-102
-***
-223
-***
-252
-()
-80
-()
-70
-()
-69
-()
-68
-()
-66
-()
-64
-()
-62
-***
-256
-()
-61
-***
-93
-()
-59
-***
-120
-()
-58
-()
-57
-***
-183
-()
-55
-()
-54
-()
-52
-***
-147
-()
-51
-***
-118
-()
-50
-***
-83
-()
-49
-***
-98
-()
-48
-***
-99
-()
-47
-()
-46
-***
-184
-()
-45
-***
-121
-()
-44
-()
-43
-***
-88
-()
-42
-***
-122
-()
-41
-***
-91
-()
-40
-***
-96
-()
-38
-***
-100
-()
-37
-***
-149
-()
-36
-***
-74
-()
-35
-***
-258
-()
-34
-***
-151
-()
-33
-***
-85
-()
-32
-()
-31
-***
-94
-()
-30
-***
-97
-()
-29
-***
-90
-()
-28
-***
-89
-()
-27
-***
-92
-()
-26
-***
-72
-***
-247
-()
-25
-***
-86
-()
-24
-***
-82
-()
-23
-***
-87
-***
-117
-()
-22
-***
-76
-***
-119
-()
-21
-***
-84
-()
-20
-***
-78
-()
-19
-***
-73
-()
-18
-***
-81
-()
-17
-***
-65
-()
-16
-***
-63
-***
-101
-()
-15
-***
-71
-()
-14
-***
-75
-()
-13
-***
-322
-()
-12
-***
-77
-()
-11
-***
-283
-()
-10
-***
-79
-()
-9
-***
-145
-***
-150
-()
-8
-***
-67
-()
-7
-***
-60
-***
-231
-()
-6
-***
-56
-***
-234
-()
-5
-***
-164
-***
-202
-()
-4
-***
-53
-()
-3
-***
-130
-***
-185
-***
-200
-()
-2
-***
-205
-()
-1
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-39
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-95
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr
deleted file mode 100755
index e45cd058f..000000000
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr
+++ /dev/null
@@ -1,2 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
deleted file mode 100755
index 902784594..000000000
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
+++ /dev/null
@@ -1,26 +0,0 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 08:47:31
-gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-
-MCF SPEC version 1.6.I
-by  Andreas Loebel
-Copyright (c) 1998,1999   ZIB Berlin
-All Rights Reserved.
-
-nodes                      : 500
-active arcs                : 1905
-simplex iterations         : 1502
-flow value                 : 4990014995
-new implicit arcs          : 23867
-active arcs                : 25772
-simplex iterations         : 2663
-flow value                 : 3080014995
-checksum                   : 68389
-optimal
-Exiting @ tick 54240666000 because target called exit()
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
deleted file mode 100644
index 66ab48bd5..000000000
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ /dev/null
@@ -1,87 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.054241                       # Number of seconds simulated
-sim_ticks                                 54240666000                       # Number of ticks simulated
-final_tick                                54240666000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2777644                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1651027932                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 342980                       # Number of bytes of host memory used
-host_seconds                                    32.85                       # Real time elapsed on the host
-sim_insts                                    91252969                       # Number of instructions simulated
-system.physmem.bytes_read                   521339715                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read              431323116                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 18908138                       # Number of bytes written to this memory
-system.physmem.num_reads                    130384074                       # Number of read requests responded to by this memory
-system.physmem.num_writes                     4738868                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     9611602391                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                7952024704                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                     348597084                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    9960199475                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        108481333                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                         91252969                       # Number of instructions executed
-system.cpu.num_int_alu_accesses              72525682                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
-system.cpu.num_func_calls                       96832                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     15127614                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     72525682                       # number of integer instructions
-system.cpu.num_fp_insts                            48                       # number of float instructions
-system.cpu.num_int_register_reads           396912516                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          106840370                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      27318811                       # number of memory refs
-system.cpu.num_load_insts                    22573967                       # Number of load instructions
-system.cpu.num_store_insts                    4744844                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  108481333                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm b/tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
deleted file mode 100644
index 9ac19076f..000000000
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
+++ /dev/null
@@ -1,4 +0,0 @@
-P6
-15 15
-255
-


			   !!!   !!!$$$&&&'''&&&%%%


!!!%%%(((******)))(((!!!###'''***+++,,,+++)))"""###''')))++++++***)))!!!!!!%%%((()))))))))'''   """%%%&&&'''&&&%%%%%%      !!!"""#########"""(((---222666&&&...///===;;;999555111,,,((($$$DDDKKKRRRXXXBBB†††‘‘‘jjjWWWZZZUUUNNNGGG???888[[[dddkkkrrr]]]CCC===eeeaaarrrkkkddd[[[SSSKKKiiipppvvvvvvEEEggg{{{uuunnnfff^^^VVVmmmsssxxx|||oooEEEDDD]]]vvvzzzuuuooohhhaaaZZZjjjooossswwwyyyzzzzzzyyywwwtttoookkkeee```ZZZeeeiiilllnnnpppppppppooonnnkkkhhhddd```\\\WWW
\ No newline at end of file
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
deleted file mode 100644
index 2f73411a5..000000000
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ /dev/null
@@ -1,205 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-memories=system.physmem
-num_work_ids=16
-physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[0]
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=262144
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.dtb]
-type=ArmTLB
-size=64
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=131072
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.itb]
-type=ArmTLB
-size=64
-
-[system.cpu.l2cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=2097152
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
-
-[system.cpu.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=mcf mcf.in
-cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
-gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=55300000000
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:268435455
-zero=false
-port=system.membus.port[1]
-
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out b/tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out
deleted file mode 100644
index 095132477..000000000
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out
+++ /dev/null
@@ -1,999 +0,0 @@
-()
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-()
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-()
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-***
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-()
-35
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-()
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-()
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-()
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-31
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-()
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-()
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-()
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-***
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-()
-27
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-()
-26
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-72
-***
-247
-()
-25
-***
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-()
-24
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-()
-23
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-87
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-22
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-21
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-()
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-16
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-()
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-14
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-13
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-283
-()
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-79
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-9
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-145
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-150
-()
-8
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-7
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-231
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-6
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-56
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-234
-()
-5
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-164
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-()
-4
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-53
-()
-3
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-130
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-()
-2
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-()
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-39
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-95
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr
deleted file mode 100755
index e45cd058f..000000000
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr
+++ /dev/null
@@ -1,2 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
deleted file mode 100755
index 959967602..000000000
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
+++ /dev/null
@@ -1,26 +0,0 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 08:48:15
-gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-
-MCF SPEC version 1.6.I
-by  Andreas Loebel
-Copyright (c) 1998,1999   ZIB Berlin
-All Rights Reserved.
-
-nodes                      : 500
-active arcs                : 1905
-simplex iterations         : 1502
-flow value                 : 4990014995
-new implicit arcs          : 23867
-active arcs                : 25772
-simplex iterations         : 2663
-flow value                 : 3080014995
-checksum                   : 68389
-optimal
-Exiting @ tick 148086239000 because target called exit()
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
deleted file mode 100644
index d6f3be234..000000000
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ /dev/null
@@ -1,280 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.148086                       # Number of seconds simulated
-sim_ticks                                148086239000                       # Number of ticks simulated
-final_tick                               148086239000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1300672                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2111359212                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 351948                       # Number of bytes of host memory used
-host_seconds                                    70.14                       # Real time elapsed on the host
-sim_insts                                    91226321                       # Number of instructions simulated
-system.physmem.bytes_read                      986112                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  36992                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     2048                       # Number of bytes written to this memory
-system.physmem.num_reads                        15408                       # Number of read requests responded to by this memory
-system.physmem.num_writes                          32                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                        6659039                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    249800                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                         13830                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                       6672869                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        296172478                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                         91226321                       # Number of instructions executed
-system.cpu.num_int_alu_accesses              72525682                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
-system.cpu.num_func_calls                       96832                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     15127614                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     72525682                       # number of integer instructions
-system.cpu.num_fp_insts                            48                       # number of float instructions
-system.cpu.num_int_register_reads           464563396                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          106840370                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      27318811                       # number of memory refs
-system.cpu.num_load_insts                    22573967                       # Number of load instructions
-system.cpu.num_store_insts                    4744844                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  296172478                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.icache.replacements                      2                       # number of replacements
-system.cpu.icache.tagsinuse                510.335448                       # Cycle average of tags in use
-system.cpu.icache.total_refs                107830181                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    599                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               180016.996661                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            510.335448                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.249187                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              107830181                       # number of ReadReq hits
-system.cpu.icache.demand_hits               107830181                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              107830181                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  599                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   599                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  599                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       32662000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        32662000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       32662000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          107830780                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           107830780                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          107830780                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000006                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000006                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000006                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 54527.545910                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 54527.545910                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 54527.545910                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             599                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              599                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             599                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     30865000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     30865000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     30865000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000006                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000006                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000006                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 51527.545910                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 942702                       # number of replacements
-system.cpu.dcache.tagsinuse               3568.549501                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 26345365                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 946798                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  27.825751                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            54479156000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           3568.549501                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.871228                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               21649219                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits               4688372                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits             3887                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits              3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits                26337591                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               26337591                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               900189                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses               46609                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                946798                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses               946798                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    12614490000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    1263542000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     13878032000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    13878032000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           22549408                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses           4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses         3887                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses          3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            27284389                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           27284389                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.039921                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.009844                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.034701                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.034701                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 14013.157237                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 14657.859438                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 14657.859438                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   942309                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          900189                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses          46609                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           946798                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          946798                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   9913923000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   1123715000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  11037638000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  11037638000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.039921                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.009844                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.034701                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.034701                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157237                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24109.399472                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11657.859438                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                   634                       # number of replacements
-system.cpu.l2cache.tagsinuse              9235.307693                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1594542                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 15392                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                103.595504                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           325.097811                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          8910.209882                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.009921                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.271918                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                899928                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              942309                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               32061                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 931989                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                931989                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 860                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             14548                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                15408                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               15408                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      44720000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency    756496000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      801216000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     801216000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            900788                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          942309                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses           46609                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             947397                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            947397                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.000955                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.312129                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.016264                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.016264                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                      32                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            860                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        14548                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           15408                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          15408                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     34400000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    581920000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    616320000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    616320000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.000955                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.312129                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.016264                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.016264                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
deleted file mode 100644
index 77055bd16..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ /dev/null
@@ -1,102 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-memories=system.physmem
-num_work_ids=16
-physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[0]
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb itb tracer workload
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
-
-[system.cpu.dtb]
-type=SparcTLB
-size=64
-
-[system.cpu.itb]
-type=SparcTLB
-size=64
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=mcf mcf.in
-cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
-gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=55300000000
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:268435455
-zero=false
-port=system.membus.port[1]
-
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
deleted file mode 100644
index 095132477..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
+++ /dev/null
@@ -1,999 +0,0 @@
-()
-500
-()
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-()
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-()
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-()
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-()
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-()
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-384
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-()
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-***
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-497
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-***
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-()
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-***
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-***
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-()
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-***
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-276
-***
-296
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-273
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-271
-()
-265
-()
-246
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-267
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-239
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-237
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-262
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-294
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-229
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-397
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-228
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-()
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-()
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-197
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-195
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-194
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-()
-193
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-274
-()
-191
-***
-203
-()
-190
-***
-263
-()
-189
-215
-***
-230
-()
-188
-***
-266
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-295
-()
-182
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-329
-()
-181
-***
-351
-()
-180
-***
-441
-()
-179
-***
-453
-()
-178
-***
-418
-()
-177
-***
-353
-()
-176
-***
-422
-()
-175
-***
-225
-***
-255
-()
-174
-***
-269
-()
-173
-***
-214
-()
-172
-***
-186
-()
-171
-***
-447
-()
-170
-***
-270
-***
-306
-()
-169
-***
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-()
-168
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-285
-()
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-146
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-()
-143
-***
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-()
-142
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-()
-141
-***
-167
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-251
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-140
-***
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-139
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-137
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-***
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-()
-132
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-213
-()
-131
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-187
-()
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-128
-***
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-127
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-()
-126
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-159
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-()
-125
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-()
-124
-***
-157
-()
-123
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-152
-()
-116
-***
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-163
-()
-115
-***
-133
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-248
-()
-114
-***
-192
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-212
-()
-113
-***
-268
-()
-112
-***
-367
-()
-111
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-()
-110
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-()
-109
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-323
-()
-108
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-281
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-148
-()
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-275
-()
-105
-***
-196
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-254
-()
-104
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-138
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-161
-()
-103
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-310
-()
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-223
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-70
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-69
-()
-68
-()
-66
-()
-64
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-62
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-120
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-57
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-54
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-52
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-51
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-49
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-48
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-99
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-46
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-121
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-44
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-43
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-88
-()
-42
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-122
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-41
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-91
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-40
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-96
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-38
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-100
-()
-37
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-()
-36
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-74
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-35
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-258
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-34
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-33
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-()
-32
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-31
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-30
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-29
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-28
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-26
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-()
-25
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-86
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-24
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-23
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-117
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-22
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-119
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-21
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-84
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-20
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-78
-()
-19
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-73
-()
-18
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-81
-()
-17
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-65
-()
-16
-***
-63
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-101
-()
-15
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-71
-()
-14
-***
-75
-()
-13
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-322
-()
-12
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-77
-()
-11
-***
-283
-()
-10
-***
-79
-()
-9
-***
-145
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-150
-()
-8
-***
-67
-()
-7
-***
-60
-***
-231
-()
-6
-***
-56
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-234
-()
-5
-***
-164
-***
-202
-()
-4
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-53
-()
-3
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-130
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-185
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-200
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-2
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-205
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-1
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-39
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-95
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr
deleted file mode 100755
index e45cd058f..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr
+++ /dev/null
@@ -1,2 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
deleted file mode 100755
index 18a19b6d7..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
+++ /dev/null
@@ -1,26 +0,0 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:20:13
-gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-
-MCF SPEC version 1.6.I
-by  Andreas Loebel
-Copyright (c) 1998,1999   ZIB Berlin
-All Rights Reserved.
-
-nodes                      : 500
-active arcs                : 1905
-simplex iterations         : 1502
-flow value                 : 4990014995
-new implicit arcs          : 23867
-active arcs                : 25772
-simplex iterations         : 2663
-flow value                 : 3080014995
-checksum                   : 68389
-optimal
-Exiting @ tick 122215830000 because target called exit()
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
deleted file mode 100644
index e3ffceab4..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.122216                       # Number of seconds simulated
-sim_ticks                                122215830000                       # Number of ticks simulated
-final_tick                               122215830000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3409932                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1709135687                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 338176                       # Number of bytes of host memory used
-host_seconds                                    71.51                       # Real time elapsed on the host
-sim_insts                                   243835278                       # Number of instructions simulated
-system.physmem.bytes_read                  1306360053                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read              977686044                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 91606089                       # Number of bytes written to this memory
-system.physmem.num_reads                    326641945                       # Number of read requests responded to by this memory
-system.physmem.num_writes                    22901951                       # Number of write requests responded to by this memory
-system.physmem.num_other                         3886                       # Number of other requests responded to by this memory
-system.physmem.bw_read                    10688959466                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                7999667834                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                     749543566                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                   11438503032                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu.workload.num_syscalls                  443                       # Number of system calls
-system.cpu.numCycles                        244431661                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        243835278                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             194726506                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                  11630                       # Number of float alu accesses
-system.cpu.num_func_calls                     4252956                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18619960                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    194726506                       # number of integer instructions
-system.cpu.num_fp_insts                         11630                       # number of float instructions
-system.cpu.num_int_register_reads           456819010                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          215451567                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                23256                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  90                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     105711442                       # number of memory refs
-system.cpu.num_load_insts                    82803522                       # Number of load instructions
-system.cpu.num_store_insts                   22907920                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  244431661                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
deleted file mode 100644
index acd41b2d5..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ /dev/null
@@ -1,205 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-memories=system.physmem
-num_work_ids=16
-physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[0]
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=262144
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.dtb]
-type=SparcTLB
-size=64
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=131072
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.itb]
-type=SparcTLB
-size=64
-
-[system.cpu.l2cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=2097152
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
-
-[system.cpu.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=mcf mcf.in
-cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
-gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=55300000000
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:268435455
-zero=false
-port=system.membus.port[1]
-
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out
deleted file mode 100644
index 095132477..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out
+++ /dev/null
@@ -1,999 +0,0 @@
-()
-500
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-499
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-498
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-496
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-346
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-483
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-()
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-()
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-()
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-()
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-()
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-()
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-()
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-()
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-()
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-()
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-***
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-()
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-()
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-***
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-()
-139
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-()
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-()
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-()
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-()
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-()
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-()
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-()
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-()
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diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr
deleted file mode 100755
index e45cd058f..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr
+++ /dev/null
@@ -1,2 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
deleted file mode 100755
index ca44a686d..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
+++ /dev/null
@@ -1,26 +0,0 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:21:35
-gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-
-MCF SPEC version 1.6.I
-by  Andreas Loebel
-Copyright (c) 1998,1999   ZIB Berlin
-All Rights Reserved.
-
-nodes                      : 500
-active arcs                : 1905
-simplex iterations         : 1502
-flow value                 : 4990014995
-new implicit arcs          : 23867
-active arcs                : 25772
-simplex iterations         : 2663
-flow value                 : 3080014995
-checksum                   : 68389
-optimal
-Exiting @ tick 362430887000 because target called exit()
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
deleted file mode 100644
index 7dc591cfe..000000000
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ /dev/null
@@ -1,244 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.362431                       # Number of seconds simulated
-sim_ticks                                362430887000                       # Number of ticks simulated
-final_tick                               362430887000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1587659                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2359857170                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 346888                       # Number of bytes of host memory used
-host_seconds                                   153.58                       # Real time elapsed on the host
-sim_insts                                   243835278                       # Number of instructions simulated
-system.physmem.bytes_read                     1001472                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  56256                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     2560                       # Number of bytes written to this memory
-system.physmem.num_reads                        15648                       # Number of read requests responded to by this memory
-system.physmem.num_writes                          40                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                        2763208                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    155219                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                          7063                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                       2770272                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu.workload.num_syscalls                  443                       # Number of system calls
-system.cpu.numCycles                        724861774                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        243835278                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             194726506                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                  11630                       # Number of float alu accesses
-system.cpu.num_func_calls                     4252956                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18619960                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    194726506                       # number of integer instructions
-system.cpu.num_fp_insts                         11630                       # number of float instructions
-system.cpu.num_int_register_reads           456819010                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          215451566                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                23256                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  90                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     105711442                       # number of memory refs
-system.cpu.num_load_insts                    82803522                       # Number of load instructions
-system.cpu.num_store_insts                   22907920                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  724861774                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.icache.replacements                     25                       # number of replacements
-system.cpu.icache.tagsinuse                725.567632                       # Cycle average of tags in use
-system.cpu.icache.total_refs                244420630                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    882                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               277120.895692                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            725.567632                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.354281                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              244420630                       # number of ReadReq hits
-system.cpu.icache.demand_hits               244420630                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              244420630                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  882                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   882                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  882                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       49266000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        49266000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       49266000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          244421512                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           244421512                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          244421512                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000004                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000004                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55857.142857                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55857.142857                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55857.142857                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             882                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              882                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             882                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     46620000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     46620000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     46620000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000004                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000004                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000004                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52857.142857                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52857.142857                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52857.142857                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 935475                       # number of replacements
-system.cpu.dcache.tagsinuse               3563.824259                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                104186700                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 939571                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 110.887522                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle           134373316000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           3563.824259                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.870074                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               81327577                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              22855241                       # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits                   3882                       # number of SwapReq hits
-system.cpu.dcache.demand_hits               104182818                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              104182818                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               892857                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses               46710                       # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses                    4                       # number of SwapReq misses
-system.cpu.dcache.demand_misses                939567                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses               939567                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    12508482000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    1265712000                       # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency          98000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency     13774194000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    13774194000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           82220434                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          22901951                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses               3886                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           105122385                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          105122385                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.010859                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.002040                       # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate          0.001029                       # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate           0.008938                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.008938                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 14009.502082                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 27097.238279                       # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency        24500                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 14660.150899                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 14660.150899                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   935237                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          892857                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses          46710                       # number of WriteReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses               4                       # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           939567                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          939567                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   9829911000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   1125582000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency        86000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  10955493000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  10955493000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.010859                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.002040                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate     0.001029                       # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.008938                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.008938                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.502082                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24097.238279                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency        21500                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11660.150899                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11660.150899                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                   865                       # number of replacements
-system.cpu.l2cache.tagsinuse              9236.752232                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1585884                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 15631                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                101.457616                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           375.506440                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          8861.245791                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.011460                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.270424                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                892658                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              935237                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               32147                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 924805                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                924805                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                1081                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             14567                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                15648                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               15648                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      56212000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency    757484000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      813696000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     813696000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            893739                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          935237                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses           46714                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             940453                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            940453                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.001210                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.311834                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.016639                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.016639                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                      40                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           1081                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        14567                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           15648                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          15648                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     43240000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    582680000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    625920000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    625920000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.001210                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.311834                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.016639                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.016639                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
deleted file mode 100644
index cfda7ba22..000000000
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ /dev/null
@@ -1,535 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-memories=system.physmem
-num_work_ids=16
-physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[0]
-
-[system.cpu]
-type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-LSQCheckLoads=true
-LSQDepCheckShift=4
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-cachePorts=200
-checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
-clock=500
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-defer_registration=false
-dispatchWidth=8
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-phase=0
-predType=tournament
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-squashWidth=8
-store_set_clear_period=250000
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbDepth=1
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=262144
-subblock_size=0
-tgts_per_mshr=20
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.dtb]
-type=X86TLB
-size=64
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=6
-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList
-count=0
-opList=system.cpu.fuPool.FUList4.opList
-
-[system.cpu.fuPool.FUList4.opList]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
-
-[system.cpu.fuPool.FUList5.opList00]
-type=OpDesc
-issueLat=1
-opClass=SimdAdd
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList01]
-type=OpDesc
-issueLat=1
-opClass=SimdAddAcc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList02]
-type=OpDesc
-issueLat=1
-opClass=SimdAlu
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList03]
-type=OpDesc
-issueLat=1
-opClass=SimdCmp
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList04]
-type=OpDesc
-issueLat=1
-opClass=SimdCvt
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList05]
-type=OpDesc
-issueLat=1
-opClass=SimdMisc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList06]
-type=OpDesc
-issueLat=1
-opClass=SimdMult
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList07]
-type=OpDesc
-issueLat=1
-opClass=SimdMultAcc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList08]
-type=OpDesc
-issueLat=1
-opClass=SimdShift
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList09]
-type=OpDesc
-issueLat=1
-opClass=SimdShiftAcc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList10]
-type=OpDesc
-issueLat=1
-opClass=SimdSqrt
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList11]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatAdd
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList12]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatAlu
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList13]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatCmp
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList14]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatCvt
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList15]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatDiv
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList16]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatMisc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList17]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatMult
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList18]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatMultAcc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList19]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatSqrt
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList7.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-opList=system.cpu.fuPool.FUList8.opList
-
-[system.cpu.fuPool.FUList8.opList]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=131072
-subblock_size=0
-tgts_per_mshr=20
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.itb]
-type=X86TLB
-size=64
-
-[system.cpu.l2cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=2097152
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
-
-[system.cpu.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=mcf mcf.in
-cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
-gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=55300000000
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:268435455
-zero=false
-port=system.membus.port[1]
-
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out b/tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out
deleted file mode 100644
index 095132477..000000000
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out
+++ /dev/null
@@ -1,999 +0,0 @@
-()
-500
-()
-499
-()
-498
-()
-496
-()
-495
-()
-494
-()
-493
-()
-492
-()
-491
-()
-490
-()
-489
-()
-488
-()
-487
-()
-486
-()
-484
-()
-482
-()
-481
-()
-480
-()
-479
-()
-478
-()
-477
-()
-476
-()
-475
-()
-474
-()
-473
-()
-472
-()
-471
-()
-469
-()
-468
-()
-467
-()
-466
-()
-465
-()
-464
-()
-463
-()
-462
-()
-461
-()
-460
-()
-459
-()
-458
-()
-457
-()
-455
-()
-454
-()
-452
-()
-451
-()
-450
-()
-449
-()
-448
-()
-446
-()
-445
-()
-444
-()
-443
-()
-442
-()
-440
-()
-439
-()
-438
-()
-436
-()
-435
-()
-433
-()
-432
-()
-431
-()
-428
-()
-427
-()
-425
-()
-424
-()
-423
-()
-420
-()
-419
-()
-416
-()
-414
-()
-413
-()
-412
-()
-407
-()
-406
-()
-405
-()
-404
-()
-403
-()
-402
-()
-401
-()
-400
-()
-399
-()
-398
-()
-396
-()
-395
-()
-393
-()
-392
-()
-390
-()
-389
-()
-388
-()
-387
-()
-386
-()
-385
-()
-384
-()
-383
-()
-382
-()
-381
-()
-380
-()
-379
-()
-377
-()
-375
-()
-374
-()
-373
-()
-372
-()
-371
-()
-370
-()
-369
-()
-368
-()
-366
-()
-365
-()
-364
-()
-362
-()
-361
-()
-360
-()
-359
-()
-358
-()
-357
-()
-356
-()
-355
-()
-354
-()
-352
-()
-350
-()
-347
-()
-344
-()
-342
-()
-341
-()
-340
-()
-339
-()
-338
-()
-332
-()
-325
-()
-320
-***
-345
-()
-319
-***
-497
-()
-318
-***
-349
-()
-317
-***
-408
-()
-316
-***
-324
-()
-315
-***
-328
-()
-314
-***
-335
-()
-313
-***
-378
-()
-312
-***
-426
-()
-311
-***
-411
-()
-304
-***
-343
-()
-303
-***
-417
-()
-302
-***
-485
-()
-301
-***
-363
-()
-300
-***
-376
-()
-299
-***
-333
-()
-292
-***
-337
-()
-291
-***
-409
-()
-290
-***
-421
-()
-289
-***
-437
-()
-288
-***
-430
-()
-287
-***
-348
-()
-286
-***
-326
-()
-284
-()
-282
-***
-308
-()
-279
-***
-297
-***
-305
-()
-278
-()
-277
-***
-307
-()
-276
-***
-296
-()
-273
-()
-271
-()
-265
-()
-246
-***
-267
-()
-245
-***
-280
-()
-244
-***
-391
-()
-243
-***
-330
-()
-242
-***
-456
-()
-241
-***
-346
-()
-240
-***
-483
-()
-239
-***
-260
-()
-238
-***
-261
-()
-237
-***
-262
-***
-294
-()
-236
-***
-253
-()
-229
-***
-397
-()
-228
-***
-298
-()
-227
-***
-415
-()
-226
-***
-264
-()
-224
-***
-232
-()
-222
-***
-233
-()
-217
-***
-250
-()
-211
-***
-331
-()
-210
-***
-394
-()
-209
-***
-410
-()
-208
-***
-321
-()
-207
-***
-327
-()
-206
-***
-309
-()
-199
-***
-259
-()
-198
-***
-219
-()
-197
-***
-220
-()
-195
-***
-429
-()
-194
-***
-470
-()
-193
-***
-274
-()
-191
-***
-203
-()
-190
-***
-263
-()
-189
-215
-***
-230
-()
-188
-***
-266
-***
-295
-()
-182
-***
-329
-()
-181
-***
-351
-()
-180
-***
-441
-()
-179
-***
-453
-()
-178
-***
-418
-()
-177
-***
-353
-()
-176
-***
-422
-()
-175
-***
-225
-***
-255
-()
-174
-***
-269
-()
-173
-***
-214
-()
-172
-***
-186
-()
-171
-***
-447
-()
-170
-***
-270
-***
-306
-()
-169
-***
-336
-()
-168
-***
-285
-()
-165
-***
-249
-()
-146
-***
-154
-()
-143
-***
-334
-()
-142
-***
-216
-***
-257
-()
-141
-***
-167
-***
-251
-()
-140
-***
-162
-***
-293
-()
-139
-***
-158
-()
-137
-***
-166
-***
-201
-()
-136
-***
-160
-()
-134
-***
-221
-()
-132
-***
-213
-()
-131
-***
-187
-()
-129
-***
-235
-()
-128
-***
-153
-()
-127
-***
-156
-()
-126
-***
-159
-***
-218
-()
-125
-***
-155
-()
-124
-***
-157
-()
-123
-***
-152
-()
-116
-***
-135
-***
-163
-()
-115
-***
-133
-***
-204
-***
-248
-()
-114
-***
-192
-***
-212
-()
-113
-***
-268
-()
-112
-***
-367
-()
-111
-***
-272
-()
-110
-***
-434
-()
-109
-***
-323
-()
-108
-***
-281
-()
-107
-***
-144
-***
-148
-()
-106
-***
-275
-()
-105
-***
-196
-***
-254
-()
-104
-***
-138
-***
-161
-()
-103
-***
-310
-()
-102
-***
-223
-***
-252
-()
-80
-()
-70
-()
-69
-()
-68
-()
-66
-()
-64
-()
-62
-***
-256
-()
-61
-***
-93
-()
-59
-***
-120
-()
-58
-()
-57
-***
-183
-()
-55
-()
-54
-()
-52
-***
-147
-()
-51
-***
-118
-()
-50
-***
-83
-()
-49
-***
-98
-()
-48
-***
-99
-()
-47
-()
-46
-***
-184
-()
-45
-***
-121
-()
-44
-()
-43
-***
-88
-()
-42
-***
-122
-()
-41
-***
-91
-()
-40
-***
-96
-()
-38
-***
-100
-()
-37
-***
-149
-()
-36
-***
-74
-()
-35
-***
-258
-()
-34
-***
-151
-()
-33
-***
-85
-()
-32
-()
-31
-***
-94
-()
-30
-***
-97
-()
-29
-***
-90
-()
-28
-***
-89
-()
-27
-***
-92
-()
-26
-***
-72
-***
-247
-()
-25
-***
-86
-()
-24
-***
-82
-()
-23
-***
-87
-***
-117
-()
-22
-***
-76
-***
-119
-()
-21
-***
-84
-()
-20
-***
-78
-()
-19
-***
-73
-()
-18
-***
-81
-()
-17
-***
-65
-()
-16
-***
-63
-***
-101
-()
-15
-***
-71
-()
-14
-***
-75
-()
-13
-***
-322
-()
-12
-***
-77
-()
-11
-***
-283
-()
-10
-***
-79
-()
-9
-***
-145
-***
-150
-()
-8
-***
-67
-()
-7
-***
-60
-***
-231
-()
-6
-***
-56
-***
-234
-()
-5
-***
-164
-***
-202
-()
-4
-***
-53
-()
-3
-***
-130
-***
-185
-***
-200
-()
-2
-***
-205
-()
-1
-***
-39
-***
-95
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simerr b/tests/long/10.mcf/ref/x86/linux/o3-timing/simerr
deleted file mode 100755
index ac4ad20a5..000000000
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simerr
+++ /dev/null
@@ -1,4 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
-warn: instruction 'fldcw_Mw' unimplemented
-hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
deleted file mode 100755
index 426afea0c..000000000
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
+++ /dev/null
@@ -1,26 +0,0 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 06:45:46
-gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-
-MCF SPEC version 1.6.I
-by  Andreas Loebel
-Copyright (c) 1998,1999   ZIB Berlin
-All Rights Reserved.
-
-nodes                      : 500
-active arcs                : 1905
-simplex iterations         : 1502
-flow value                 : 4990014995
-new implicit arcs          : 23867
-active arcs                : 25772
-simplex iterations         : 2663
-flow value                 : 3080014995
-checksum                   : 68389
-optimal
-Exiting @ tick 70312944500 because target called exit()
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
deleted file mode 100644
index f9c970889..000000000
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ /dev/null
@@ -1,486 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.070313                       # Number of seconds simulated
-sim_ticks                                 70312944500                       # Number of ticks simulated
-final_tick                                70312944500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 168126                       # Simulator instruction rate (inst/s)
-host_tick_rate                               42493747                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 349904                       # Number of bytes of host memory used
-host_seconds                                  1654.67                       # Real time elapsed on the host
-sim_insts                                   278192519                       # Number of instructions simulated
-system.physmem.bytes_read                     4896576                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  65344                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                  1867840                       # Number of bytes written to this memory
-system.physmem.num_reads                        76509                       # Number of read requests responded to by this memory
-system.physmem.num_writes                       29185                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       69639752                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    929331                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      26564668                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      96204419                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        140625890                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 37833804                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           37833804                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            1322933                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              33591925                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 33081589                       # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           29087381                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      203627812                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    37833804                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33081589                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      63297987                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                10276298                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               38195582                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   21                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles            95                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  28266291                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                204981                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          139497150                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.574262                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.291399                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 78673130     56.40%     56.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3606277      2.59%     58.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2810090      2.01%     61.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  4532102      3.25%     64.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  6824412      4.89%     69.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  5279008      3.78%     72.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  7637539      5.48%     78.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  4315201      3.09%     81.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 25819391     18.51%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            139497150                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.269039                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.448011                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 41917744                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              28560060                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  52643719                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               7459543                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                8916084                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              354657218                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                8916084                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 48823983                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4469241                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           6888                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  53004642                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              24276312                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              350176569                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    14                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 101342                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              20289844                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           314446851                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             861231533                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        861227904                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              3629                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             248344192                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 66102659                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                479                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            472                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  56104077                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            112666461                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            37647255                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          48253520                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          8188094                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  343455788                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                2295                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 316242386                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             89834                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        65098177                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     92870721                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1849                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     139497150                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.267017                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.750973                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            31795649     22.79%     22.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            18418675     13.20%     36.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            25717845     18.44%     54.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            29872112     21.41%     75.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            18507796     13.27%     89.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            10200782      7.31%     96.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             3199934      2.29%     98.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1737869      1.25%     99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8               46488      0.03%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       139497150                       # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   25785      1.36%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1795857     94.47%     95.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                 79349      4.17%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass             16711      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             180262574     57.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 195      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            101451147     32.08%     89.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            34511759     10.91%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              316242386                       # Type of FU issued
-system.cpu.iq.rate                           2.248821                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1900991                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006011                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          773971833                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         408587092                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    312537049                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 914                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               2332                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          382                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              318126211                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     455                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         45906656                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     21887073                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       122159                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        33758                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6207504                       # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         2763                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         15488                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                8916084                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  901068                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 88602                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           343458083                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             26305                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             112666461                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             37647255                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                465                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   1597                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 48733                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          33758                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1219939                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       230098                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1450037                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             314144155                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             100864248                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2098231                       # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    134973322                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31810521                       # Number of branches executed
-system.cpu.iew.exec_stores                   34109074                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.233900                       # Inst execution rate
-system.cpu.iew.wb_sent                      313190495                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     312537431                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 232392592                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 318468890                       # num instructions consuming a value
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.222474                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.729718                       # average fanout of values written-back
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      278192519                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        65270328                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls             446                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1322946                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    130581066                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.130420                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.663472                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     50414718     38.61%     38.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     24339651     18.64%     57.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     16499074     12.64%     69.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     12376450      9.48%     79.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3696747      2.83%     82.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      3466084      2.65%     84.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      2761727      2.11%     86.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1175320      0.90%     87.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     15851295     12.14%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    130581066                       # Number of insts commited each cycle
-system.cpu.commit.count                     278192519                       # Number of instructions committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      122219139                       # Number of memory references committed
-system.cpu.commit.loads                      90779388                       # Number of loads committed
-system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.branches                   29309710                       # Number of branches committed
-system.cpu.commit.fp_insts                         40                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 278186227                       # Number of committed integer instructions.
-system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              15851295                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    458192618                       # The number of ROB reads
-system.cpu.rob.rob_writes                   695856607                       # The number of ROB writes
-system.cpu.timesIdled                           33615                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         1128740                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   278192519                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             278192519                       # Number of Instructions Simulated
-system.cpu.cpi                               0.505498                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.505498                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.978245                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.978245                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                554794614                       # number of integer regfile reads
-system.cpu.int_regfile_writes               279836675                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       437                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      335                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               201195947                       # number of misc regfile reads
-system.cpu.icache.replacements                     68                       # number of replacements
-system.cpu.icache.tagsinuse                824.679926                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 28264985                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   1027                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               27521.893866                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            824.679926                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.402676                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               28264985                       # number of ReadReq hits
-system.cpu.icache.demand_hits                28264985                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               28264985                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1306                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1306                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1306                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       47073500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        47073500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       47073500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           28266291                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            28266291                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           28266291                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000046                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000046                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000046                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36044.027565                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36044.027565                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36044.027565                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               278                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                278                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               278                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            1028                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             1028                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            1028                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     36154500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     36154500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     36154500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000036                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000036                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000036                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35169.747082                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35169.747082                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35169.747082                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2073066                       # number of replacements
-system.cpu.dcache.tagsinuse               4076.005888                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 83808707                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2077162                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  40.347699                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            23845092000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4076.005888                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.995119                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               52611944                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              31196754                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                83808698                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               83808698                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              2262875                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              242997                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               2505872                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2505872                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    14629803500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    4394648436                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     19024451936                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    19024451936                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           54874819                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          31439751                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            86314570                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           86314570                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.041237                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.007729                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.029032                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.029032                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency  6465.139922                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 18085.196262                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency  7591.948805                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency  7591.948805                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       289000                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                92                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  3141.304348                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  1447147                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            291175                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits           137531                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits             428706                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits            428706                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1971700                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         105466                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          2077166                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         2077166                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   5609142000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   1870309936                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   7479451936                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   7479451936                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.035931                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.003355                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.024065                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.024065                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2844.825278                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17733.771414                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  3600.796439                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  3600.796439                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                 49057                       # number of replacements
-system.cpu.l2cache.tagsinuse             18859.305089                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 3318010                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 77063                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                 43.055811                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          6747.919367                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         12111.385721                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.205930                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.369610                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               1938157                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             1447147                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               63526                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                2001683                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               2001683                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               34474                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses                1                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses             42035                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                76509                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               76509                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1179443000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   1438838000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     2618281000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    2618281000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1972631                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         1447147                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses              1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          105561                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            2078192                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           2078192                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.017476                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.398206                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.036815                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.036815                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34212.536984                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34229.523017                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34221.869323                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34221.869323                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs        37500                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs               14                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  2678.571429                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   29185                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          34474                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        42035                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           76509                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          76509                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1069429500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency        31000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1307209000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   2376638500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   2376638500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.017476                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.398206                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.036815                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.036815                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.334919                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31098.108719                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31063.515403                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31063.515403                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
deleted file mode 100644
index 96706c5cc..000000000
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ /dev/null
@@ -1,102 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-memories=system.physmem
-num_work_ids=16
-physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[0]
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb itb tracer workload
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
-
-[system.cpu.dtb]
-type=X86TLB
-size=64
-
-[system.cpu.itb]
-type=X86TLB
-size=64
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=mcf mcf.in
-cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
-gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=55300000000
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:268435455
-zero=false
-port=system.membus.port[1]
-
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out b/tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out
deleted file mode 100644
index 095132477..000000000
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out
+++ /dev/null
@@ -1,999 +0,0 @@
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-19
-***
-73
-()
-18
-***
-81
-()
-17
-***
-65
-()
-16
-***
-63
-***
-101
-()
-15
-***
-71
-()
-14
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-75
-()
-13
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-322
-()
-12
-***
-77
-()
-11
-***
-283
-()
-10
-***
-79
-()
-9
-***
-145
-***
-150
-()
-8
-***
-67
-()
-7
-***
-60
-***
-231
-()
-6
-***
-56
-***
-234
-()
-5
-***
-164
-***
-202
-()
-4
-***
-53
-()
-3
-***
-130
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-185
-***
-200
-()
-2
-***
-205
-()
-1
-***
-39
-***
-95
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr
deleted file mode 100755
index ac4ad20a5..000000000
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr
+++ /dev/null
@@ -1,4 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
-warn: instruction 'fldcw_Mw' unimplemented
-hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
deleted file mode 100755
index eb189c10a..000000000
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
+++ /dev/null
@@ -1,26 +0,0 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 06:52:52
-gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-
-MCF SPEC version 1.6.I
-by  Andreas Loebel
-Copyright (c) 1998,1999   ZIB Berlin
-All Rights Reserved.
-
-nodes                      : 500
-active arcs                : 1905
-simplex iterations         : 1502
-flow value                 : 4990014995
-new implicit arcs          : 23867
-active arcs                : 25772
-simplex iterations         : 2663
-flow value                 : 3080014995
-checksum                   : 68389
-optimal
-Exiting @ tick 168950072000 because target called exit()
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
deleted file mode 100644
index e99e16cd0..000000000
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.168950                       # Number of seconds simulated
-sim_ticks                                168950072000                       # Number of ticks simulated
-final_tick                               168950072000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2042288                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1240309006                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 339312                       # Number of bytes of host memory used
-host_seconds                                   136.22                       # Real time elapsed on the host
-sim_insts                                   278192520                       # Number of instructions simulated
-system.physmem.bytes_read                  2458815679                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read             1741569664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                243173115                       # Number of bytes written to this memory
-system.physmem.num_reads                    308475658                       # Number of read requests responded to by this memory
-system.physmem.num_writes                    31439751                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                    14553504772                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read               10308191310                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                    1439319393                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                   15992824164                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        337900145                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        278192520                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             278186228                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     40                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18628012                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    278186228                       # number of integer instructions
-system.cpu.num_fp_insts                            40                       # number of float instructions
-system.cpu.num_int_register_reads           685043114                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          248344166                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                   40                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  26                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     122219139                       # number of memory refs
-system.cpu.num_load_insts                    90779388                       # Number of load instructions
-system.cpu.num_store_insts                   31439751                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  337900145                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
deleted file mode 100644
index 008adeebb..000000000
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ /dev/null
@@ -1,205 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-memories=system.physmem
-num_work_ids=16
-physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[0]
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=262144
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.dtb]
-type=X86TLB
-size=64
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=131072
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.itb]
-type=X86TLB
-size=64
-
-[system.cpu.l2cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=2097152
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
-
-[system.cpu.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=mcf mcf.in
-cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
-gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=55300000000
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:268435455
-zero=false
-port=system.membus.port[1]
-
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out b/tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out
deleted file mode 100644
index 095132477..000000000
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out
+++ /dev/null
@@ -1,999 +0,0 @@
-()
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-333
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-337
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-348
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-326
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-297
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-280
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-391
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-330
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-346
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-483
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-260
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-298
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-309
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-259
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-470
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-274
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-191
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-190
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-263
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-189
-215
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-230
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-188
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-266
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-182
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-181
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-351
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-180
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-174
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-173
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-172
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-186
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-169
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-285
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-146
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-334
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-142
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-216
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-257
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-141
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-167
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-251
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-140
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-162
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-293
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-139
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-160
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-221
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-132
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-235
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-128
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-126
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-159
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-125
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-124
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-123
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-116
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-135
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-163
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-115
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-204
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-248
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-114
-***
-192
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-113
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-268
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-112
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-367
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-108
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-106
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-104
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-103
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-252
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-80
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-57
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-55
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-54
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-51
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-50
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-83
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-49
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-98
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-48
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-46
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-45
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-44
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-43
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-42
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-41
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-91
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-38
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-37
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-36
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-85
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-31
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-28
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-26
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-25
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-23
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-22
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-21
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-19
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-73
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-81
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-17
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-16
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-63
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-101
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-15
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-71
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-14
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-75
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-13
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-322
-()
-12
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-77
-()
-11
-***
-283
-()
-10
-***
-79
-()
-9
-***
-145
-***
-150
-()
-8
-***
-67
-()
-7
-***
-60
-***
-231
-()
-6
-***
-56
-***
-234
-()
-5
-***
-164
-***
-202
-()
-4
-***
-53
-()
-3
-***
-130
-***
-185
-***
-200
-()
-2
-***
-205
-()
-1
-***
-39
-***
-95
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr b/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr
deleted file mode 100755
index ac4ad20a5..000000000
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr
+++ /dev/null
@@ -1,4 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
-warn: instruction 'fldcw_Mw' unimplemented
-hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
deleted file mode 100755
index e89b51a20..000000000
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
+++ /dev/null
@@ -1,26 +0,0 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 06:55:19
-gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-
-MCF SPEC version 1.6.I
-by  Andreas Loebel
-Copyright (c) 1998,1999   ZIB Berlin
-All Rights Reserved.
-
-nodes                      : 500
-active arcs                : 1905
-simplex iterations         : 1502
-flow value                 : 4990014995
-new implicit arcs          : 23867
-active arcs                : 25772
-simplex iterations         : 2663
-flow value                 : 3080014995
-checksum                   : 68389
-optimal
-Exiting @ tick 370010840000 because target called exit()
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
deleted file mode 100644
index 59ae818d2..000000000
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ /dev/null
@@ -1,234 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  0.370011                       # Number of seconds simulated
-sim_ticks                                370010840000                       # Number of ticks simulated
-final_tick                               370010840000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1163147                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1547047043                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 348152                       # Number of bytes of host memory used
-host_seconds                                   239.17                       # Real time elapsed on the host
-sim_insts                                   278192520                       # Number of instructions simulated
-system.physmem.bytes_read                     4900800                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  51712                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                  1885440                       # Number of bytes written to this memory
-system.physmem.num_reads                        76575                       # Number of read requests responded to by this memory
-system.physmem.num_writes                       29460                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       13245017                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    139758                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       5095634                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      18340652                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        740021680                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        278192520                       # Number of instructions executed
-system.cpu.num_int_alu_accesses             278186228                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                     40                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18628012                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    278186228                       # number of integer instructions
-system.cpu.num_fp_insts                            40                       # number of float instructions
-system.cpu.num_int_register_reads           685043114                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          248344166                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads                   40                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  26                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     122219139                       # number of memory refs
-system.cpu.num_load_insts                    90779388                       # Number of load instructions
-system.cpu.num_store_insts                   31439751                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  740021680                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.icache.replacements                     24                       # number of replacements
-system.cpu.icache.tagsinuse                666.191948                       # Cycle average of tags in use
-system.cpu.icache.total_refs                217695401                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    808                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               269425.001238                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            666.191948                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.325289                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              217695401                       # number of ReadReq hits
-system.cpu.icache.demand_hits               217695401                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              217695401                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  808                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   808                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  808                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       45248000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        45248000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       45248000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          217696209                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           217696209                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          217696209                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000004                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000004                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             808                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              808                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             808                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     42824000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     42824000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     42824000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000004                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000004                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000004                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2062733                       # number of replacements
-system.cpu.dcache.tagsinuse               4076.661903                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                120152372                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2066829                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  58.133678                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle           126200130000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4076.661903                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.995279                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               88818730                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              31333642                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               120152372                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              120152372                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              1960720                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              106109                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               2066829                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2066829                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    28849058000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    3268793000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     32117851000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    32117851000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           90779450                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          31439751                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           122219201                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          122219201                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.021599                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.003375                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.016911                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.016911                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 15539.675029                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 15539.675029                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  1437080                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1960720                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         106109                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          2066829                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         2066829                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  22966898000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   2950464500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  25917362500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  25917362500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.021599                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.003375                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.016911                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.016911                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                 49212                       # number of replacements
-system.cpu.l2cache.tagsinuse             18614.603260                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 3296079                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 77127                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                 42.735735                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          6551.798271                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         12062.804989                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.199945                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.368128                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               1927411                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             1437080                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               63651                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                1991062                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               1991062                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               34117                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             42458                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                76575                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               76575                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1774084000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   2207845500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     3981929500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    3981929500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1961528                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         1437080                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          106109                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            2067637                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           2067637                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.017393                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.400136                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.037035                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.037035                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000.385243                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000.385243                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   29460                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          34117                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        42458                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           76575                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          76575                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1364680000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1698320000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   3063000000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   3063000000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.017393                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.400136                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.037035                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.037035                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------