diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:22 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:22 -0500 |
| commit | 63eb337b3b93ab71ab3157ec6487901d4fc6cda6 (patch) | |
| tree | f3dada322d407488b3081a6b9139948b42a610b3 /tests/long/10.mcf/ref | |
| parent | ccaaa98b4916f730e5eee0cb1d206dca21cb802d (diff) | |
| download | gem5-63eb337b3b93ab71ab3157ec6487901d4fc6cda6.tar.xz | |
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
Diffstat (limited to 'tests/long/10.mcf/ref')
9 files changed, 538 insertions, 515 deletions
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini index 9285fee06..a74b5cf43 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -115,6 +115,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -413,6 +414,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -448,6 +450,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 @@ -493,9 +496,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout index 09f9f450a..69008c385 100755 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 21 2011 14:34:16 -M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch -M5 started Feb 21 2011 15:32:42 +M5 compiled Mar 11 2011 20:10:09 +M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch +M5 started Mar 11 2011 21:03:35 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 56054651500 because target called exit() +Exiting @ tick 45750115000 because target called exit() diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt index 1e441ade1..012c275ff 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,130 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 61070 # Simulator instruction rate (inst/s) -host_mem_usage 389424 # Number of bytes of host memory used -host_seconds 1493.21 # Real time elapsed on the host -host_tick_rate 37539692 # Simulator tick rate (ticks/s) +host_inst_rate 113142 # Simulator instruction rate (inst/s) +host_mem_usage 388016 # Number of bytes of host memory used +host_seconds 806.51 # Real time elapsed on the host +host_tick_rate 56726347 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 91190126 # Number of instructions simulated -sim_seconds 0.056055 # Number of seconds simulated -sim_ticks 56054651500 # Number of ticks simulated +sim_insts 91249480 # Number of instructions simulated +sim_seconds 0.045750 # Number of seconds simulated +sim_ticks 45750115000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 20717897 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 22133091 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1885129 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 22369140 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 22369140 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 18672384 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 365813 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 25060777 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 26802034 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 13379 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1583014 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 23911601 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 29845348 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 62467 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 18706972 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 599512 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 109380669 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.833810 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.220279 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 85858585 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.062935 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.459577 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 55493600 50.73% 50.73% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 34988153 31.99% 82.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 8951302 8.18% 90.91% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 6346851 5.80% 96.71% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 1763725 1.61% 98.32% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 198423 0.18% 98.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 611708 0.56% 99.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 661094 0.60% 99.67% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 365813 0.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 40879742 47.61% 47.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 22675219 26.41% 74.02% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 9677073 11.27% 85.29% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 7600715 8.85% 94.15% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2662481 3.10% 97.25% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 219814 0.26% 97.50% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 922714 1.07% 98.58% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 621315 0.72% 99.30% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 599512 0.70% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 109380669 # Number of insts commited each cycle -system.cpu.commit.COM:count 91202735 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 85858585 # Number of insts commited each cycle +system.cpu.commit.COM:count 91262089 # Number of instructions committed system.cpu.commit.COM:fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu.commit.COM:int_insts 72483223 # Number of committed integer instructions. -system.cpu.commit.COM:loads 22585492 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 27330336 # Number of memory references committed +system.cpu.commit.COM:function_calls 56148 # Number of function calls committed. +system.cpu.commit.COM:int_insts 72532978 # Number of committed integer instructions. +system.cpu.commit.COM:loads 22575791 # Number of loads committed +system.cpu.commit.COM:membars 3888 # Number of memory barriers committed +system.cpu.commit.COM:refs 27322459 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1941617 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 91202735 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 544722 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 11836562 # The number of squashed insts skipped by commit -system.cpu.committedInsts 91190126 # Number of Instructions Simulated -system.cpu.committedInsts_total 91190126 # Number of Instructions Simulated -system.cpu.cpi 1.229402 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.229402 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 23356359 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5257.244166 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2204.745551 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 22405801 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4997315500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.040698 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 950558 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 47017 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1992078000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.038685 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 903541 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 4738868 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 21505.165872 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20098.081505 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 4602377 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2935261595 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.028802 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 136491 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 89917 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 936048048 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009828 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 46574 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2906.794309 # average number of cycles each access was blocked +system.cpu.commit.branchMispredicts 1602069 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 91262089 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 554321 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 39090054 # The number of squashed insts skipped by commit +system.cpu.committedInsts 91249480 # Number of Instructions Simulated +system.cpu.committedInsts_total 91249480 # Number of Instructions Simulated +system.cpu.cpi 1.002748 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.002748 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 6707 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 17642.857143 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_hits 6700 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 123500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.001044 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.ReadReq_accesses 24501880 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5328.400499 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2255.904510 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23546851 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5088777000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.038978 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 955029 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 51059 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2039270000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.036894 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 903970 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 5711 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 5711 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 24088.951664 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 22495.719344 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 4561444 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4180324405 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.036650 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 173537 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 127274 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1040719464 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009770 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 46263 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2889.691936 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 28.426220 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 6009 # number of cycles access was blocked +system.cpu.dcache.avg_refs 29.593485 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 7453 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 17466927 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 21536874 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 28095227 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7297.350069 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3081.864877 # average overall mshr miss latency -system.cpu.dcache.demand_hits 27008178 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7932577095 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.038692 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1087049 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 136934 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 2928126048 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.033818 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 950115 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 29236861 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 8213.167334 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3241.299201 # average overall mshr miss latency +system.cpu.dcache.demand_hits 28108295 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 9269101405 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.038601 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1128566 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 178333 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3079989464 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.032501 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 950233 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.851200 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 3486.513459 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 28095227 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7297.350069 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3081.864877 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.852939 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 3493.638101 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 29236861 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 8213.167334 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3241.299201 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 27008178 # number of overall hits -system.cpu.dcache.overall_miss_latency 7932577095 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.038692 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1087049 # number of overall misses -system.cpu.dcache.overall_mshr_hits 136934 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 2928126048 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.033818 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 950115 # number of overall MSHR misses +system.cpu.dcache.overall_hits 28108295 # number of overall hits +system.cpu.dcache.overall_miss_latency 9269101405 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.038601 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1128566 # number of overall misses +system.cpu.dcache.overall_mshr_hits 178333 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3079989464 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.032501 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 950233 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 946019 # number of replacements -system.cpu.dcache.sampled_refs 950115 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 946137 # number of replacements +system.cpu.dcache.sampled_refs 950233 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3486.513459 # Cycle average of tags in use -system.cpu.dcache.total_refs 27008178 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 23888324000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 943195 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 6646243 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 108354440 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 27877036 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 74250519 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2697135 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 606870 # Number of cycles decode is unblocking +system.cpu.dcache.tagsinuse 3493.638101 # Cycle average of tags in use +system.cpu.dcache.total_refs 28120706 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 19296981000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 943150 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 18515611 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 9136 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4758893 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 141080898 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 33469255 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 33017602 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 5612232 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 30592 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 856116 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -146,243 +158,243 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 22369140 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 12683528 # Number of cache lines fetched -system.cpu.fetch.Cycles 76804780 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 214312 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 109645002 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 18268 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 1945739 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.199530 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 12683528 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 20717897 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.978019 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 112077803 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.986563 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.108841 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 29845348 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 15520576 # Number of cache lines fetched +system.cpu.fetch.Cycles 34753915 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 276813 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 143294690 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 20423 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1615761 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.326178 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 15520576 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 25123244 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.566058 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 91470816 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.578120 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.573721 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 35656347 31.81% 31.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 60887079 54.33% 86.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7618220 6.80% 92.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 828250 0.74% 93.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4141725 3.70% 97.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2560072 2.28% 99.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 241812 0.22% 99.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 9014 0.01% 99.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 135284 0.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 56780865 62.08% 62.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6426529 7.03% 69.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6459161 7.06% 76.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4449430 4.86% 81.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3594685 3.93% 84.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1897731 2.07% 87.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1934782 2.12% 89.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3238407 3.54% 92.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6689226 7.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 112077803 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 75 # number of floating regfile reads -system.cpu.fp_regfile_writes 47 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 12683528 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36327.096774 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34505.200594 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 12682753 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 28153500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 775 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 102 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 23222000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000053 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 673 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 91470816 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 87 # number of floating regfile reads +system.cpu.fp_regfile_writes 78 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 15520576 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35610.047847 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34405.604720 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 15519740 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 29770000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000054 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 836 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 158 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 23327000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000044 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 678 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 18845.101040 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 22890.471976 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 12683528 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36327.096774 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34505.200594 # average overall mshr miss latency -system.cpu.icache.demand_hits 12682753 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 28153500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses -system.cpu.icache.demand_misses 775 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 102 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 23222000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000053 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 673 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 15520576 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35610.047847 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34405.604720 # average overall mshr miss latency +system.cpu.icache.demand_hits 15519740 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 29770000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000054 # miss rate for demand accesses +system.cpu.icache.demand_misses 836 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 158 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 23327000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000044 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 678 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.278329 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 570.018353 # Average occupied blocks per context -system.cpu.icache.overall_accesses 12683528 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36327.096774 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34505.200594 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.276985 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 567.265894 # Average occupied blocks per context +system.cpu.icache.overall_accesses 15520576 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35610.047847 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34405.604720 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 12682753 # number of overall hits -system.cpu.icache.overall_miss_latency 28153500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses -system.cpu.icache.overall_misses 775 # number of overall misses -system.cpu.icache.overall_mshr_hits 102 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 23222000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 673 # number of overall MSHR misses +system.cpu.icache.overall_hits 15519740 # number of overall hits +system.cpu.icache.overall_miss_latency 29770000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000054 # miss rate for overall accesses +system.cpu.icache.overall_misses 836 # number of overall misses +system.cpu.icache.overall_mshr_hits 158 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 23327000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000044 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 678 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.sampled_refs 673 # Sample count of references to valid blocks. +system.cpu.icache.replacements 2 # number of replacements +system.cpu.icache.sampled_refs 678 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 570.018353 # Cycle average of tags in use -system.cpu.icache.total_refs 12682753 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 567.265894 # Cycle average of tags in use +system.cpu.icache.total_refs 15519740 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 31501 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 19532471 # Number of branches executed -system.cpu.iew.EXEC:nop 62748 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.868101 # Inst execution rate -system.cpu.iew.EXEC:refs 28649527 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 5007239 # Number of stores executed +system.cpu.idleCycles 29415 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 20970115 # Number of branches executed +system.cpu.iew.EXEC:nop 54598 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.133641 # Inst execution rate +system.cpu.iew.EXEC:refs 30199659 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 5140774 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 90073370 # num instructions consuming a value -system.cpu.iew.WB:count 96561407 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.596775 # average fanout of values written-back +system.cpu.iew.WB:consumers 127211016 # num instructions consuming a value +system.cpu.iew.WB:count 102056385 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.487951 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 53753580 # num instructions producing a value -system.cpu.iew.WB:rate 0.861315 # insts written-back per cycle -system.cpu.iew.WB:sent 96831306 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2055858 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 89156 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 24681129 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 553822 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1090186 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 5533282 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 103041042 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 23642288 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2270342 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 97322249 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1607 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 62072763 # num instructions producing a value +system.cpu.iew.WB:rate 1.115368 # insts written-back per cycle +system.cpu.iew.WB:sent 102572716 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 1825852 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 421320 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 32016564 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 690308 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 299404 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 6585994 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 130352707 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 25058885 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2046100 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 103728443 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 170905 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2697135 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 23177 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 1567 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 5612232 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 206705 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 17440 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 113868 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 30334 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 21484 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 353411 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 19757 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 1330 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2095636 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 788438 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 1330 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 76110 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1979748 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 246243554 # number of integer regfile reads -system.cpu.int_regfile_writes 76222698 # number of integer regfile writes -system.cpu.ipc 0.813404 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.813404 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 3168 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 9440772 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1839326 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 3168 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 298332 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1527520 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 259522598 # number of integer regfile reads +system.cpu.int_regfile_writes 80481877 # number of integer regfile writes +system.cpu.ipc 0.997260 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.997260 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 70280458 70.57% 70.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 10479 0.01% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 2 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 11 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 27 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 3 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 70.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 24261777 24.36% 94.94% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 5039834 5.06% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 74292294 70.24% 70.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 10639 0.01% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 1 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 21 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 38 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 4 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 70.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 26262906 24.83% 95.08% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 5208640 4.92% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 99592591 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 491330 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.004933 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 105774543 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 160185 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.001514 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 430175 87.55% 87.55% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 27 0.01% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 87.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 26408 5.37% 92.93% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 34720 7.07% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 52262 32.63% 32.63% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 27 0.02% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 32.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 62957 39.30% 71.95% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 44939 28.05% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 112077803 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.888602 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.089642 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 91470816 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.156375 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.444584 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 47855391 42.70% 42.70% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 42755359 38.15% 80.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 14035968 12.52% 93.37% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 4551717 4.06% 97.43% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 786660 0.70% 98.13% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 736099 0.66% 98.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1220793 1.09% 99.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 128276 0.11% 99.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 7540 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 39774696 43.48% 43.48% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 24298391 26.56% 70.05% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 14242553 15.57% 85.62% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 6365982 6.96% 92.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 2257550 2.47% 95.05% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 2688100 2.94% 97.98% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 1607594 1.76% 99.74% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 110764 0.12% 99.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 125186 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 112077803 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.888353 # Inst issue rate -system.cpu.iq.fp_alu_accesses 74 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 144 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 100083847 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 311754559 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 96561341 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 112732108 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 102424472 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 99592591 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 553822 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9752691 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 388 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 9100 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 13565681 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 91470816 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.156003 # Inst issue rate +system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 190 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 87 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 166 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 105934631 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 303205662 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 102056298 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 169015166 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 129602907 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 105774543 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 695202 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 38714982 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 25765 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 140881 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 72800988 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -404,106 +416,107 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 46574 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34284.629133 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31026.465938 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 32027 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 498738500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.312342 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 14547 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 451342000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.312342 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 14547 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 904214 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34295.295295 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.850051 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 903215 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 34261000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.001105 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 999 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 30699500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001092 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 987 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 943195 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 943195 # number of Writeback hits +system.cpu.l2cache.ReadExReq_accesses 46263 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34215.214251 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31037.691726 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 31724 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 497455000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.314268 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 14539 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 451257000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.314268 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 14539 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 904648 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34281.219272 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31102.589641 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 903631 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 34864000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.001124 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1017 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 13 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 31227000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001110 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1004 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 943150 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 943150 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 103.008184 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 102.932573 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 950788 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34285.314550 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31031.382773 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 935242 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 532999500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.016351 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 15546 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 482041500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.016338 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 15534 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_accesses 950911 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34219.529442 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31041.883806 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 935355 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 532319000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.016359 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 15556 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 482484000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.016345 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 15543 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.012324 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.246682 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 403.843587 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 8083.268197 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 950788 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34285.314550 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31031.382773 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.012326 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.249116 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 403.905799 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 8163.029985 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 950911 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34219.529442 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31041.883806 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 935242 # number of overall hits -system.cpu.l2cache.overall_miss_latency 532999500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.016351 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 15546 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 482041500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.016338 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 15534 # number of overall MSHR misses +system.cpu.l2cache.overall_hits 935355 # number of overall hits +system.cpu.l2cache.overall_miss_latency 532319000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.016359 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 15556 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 13 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 482484000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.016345 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 15543 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 709 # number of replacements -system.cpu.l2cache.sampled_refs 15518 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 704 # number of replacements +system.cpu.l2cache.sampled_refs 15528 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8487.111783 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1598481 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 8566.935784 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1598337 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 32 # number of writebacks -system.cpu.memDep0.conflictingLoads 436025 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 249497 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 24681129 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5533282 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 157552597 # number of misc regfile reads -system.cpu.misc_regfile_writes 1603309 # number of misc regfile writes -system.cpu.numCycles 112109304 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 1440720 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1005315 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 32016564 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6585994 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 198555291 # number of misc regfile reads +system.cpu.misc_regfile_writes 1603310 # number of misc regfile writes +system.cpu.numCycles 91500231 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 294826 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 72061910 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 4906 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 29931132 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 31548 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 277443671 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 106593764 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 83924752 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 72730204 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2697135 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 723329 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 11862839 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 474 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 277443197 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 5701177 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 592742 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 1065555 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 576556 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 212048419 # The number of ROB reads -system.cpu.rob.rob_writes 208775892 # The number of ROB writes -system.cpu.timesIdled 1292 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:BlockCycles 3003526 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 72121263 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 2932731 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 36158864 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2288265 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 58 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 352780022 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 136654080 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 107391797 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 31135789 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 5612232 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 6274602 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 35270531 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 655 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 352779367 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 9285803 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 702152 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 13506306 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 702838 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 215605482 # The number of ROB reads +system.cpu.rob.rob_writes 266316908 # The number of ROB writes +system.cpu.timesIdled 1399 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 442 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini index a584d29ed..febb3dd2f 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -66,9 +66,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout index 34dd3ff53..4df99b9a8 100755 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:56:16 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:56:24 -M5 executing on burrito +M5 compiled Mar 11 2011 20:10:09 +M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch +M5 started Mar 11 2011 20:10:13 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 54215549000 because target called exit() +Exiting @ tick 54240666000 because target called exit() diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 0d4b35c47..60359959c 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 937948 # Simulator instruction rate (inst/s) -host_mem_usage 362060 # Number of bytes of host memory used -host_seconds 97.24 # Real time elapsed on the host -host_tick_rate 557562760 # Simulator tick rate (ticks/s) +host_inst_rate 1915165 # Simulator instruction rate (inst/s) +host_mem_usage 378952 # Number of bytes of host memory used +host_seconds 47.65 # Real time elapsed on the host +host_tick_rate 1138365446 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 91202735 # Number of instructions simulated -sim_seconds 0.054216 # Number of seconds simulated -sim_ticks 54215549000 # Number of ticks simulated +sim_insts 91252969 # Number of instructions simulated +sim_seconds 0.054241 # Number of seconds simulated +sim_ticks 54240666000 # Number of ticks simulated system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -52,24 +52,24 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 108431099 # number of cpu cycles simulated +system.cpu.numCycles 108481333 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 108431099 # Number of busy cycles -system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_busy_cycles 108481333 # Number of busy cycles +system.cpu.num_conditional_control_insts 15112201 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_fp_insts 48 # number of float instructions system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 97900 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 91202735 # Number of instructions executed -system.cpu.num_int_alu_accesses 72483223 # Number of integer alu accesses -system.cpu.num_int_insts 72483223 # number of integer instructions -system.cpu.num_int_register_reads 234567931 # number of times the integer registers were read -system.cpu.num_int_register_writes 72546720 # number of times the integer registers were written -system.cpu.num_load_insts 22585492 # Number of load instructions -system.cpu.num_mem_refs 27330336 # number of memory refs +system.cpu.num_insts 91252969 # Number of instructions executed +system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses +system.cpu.num_int_insts 72525682 # number of integer instructions +system.cpu.num_int_register_reads 234656737 # number of times the integer registers were read +system.cpu.num_int_register_writes 72596953 # number of times the integer registers were written +system.cpu.num_load_insts 22573967 # Number of load instructions +system.cpu.num_mem_refs 27318811 # number of memory refs system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.workload.PROG:num_syscalls 442 # Number of system calls diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini index d7d6a4868..faf8a693c 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 @@ -166,9 +169,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout index b290f1d74..fff5a35b0 100755 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:56:16 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:56:25 -M5 executing on burrito +M5 compiled Mar 11 2011 20:10:09 +M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch +M5 started Mar 11 2011 21:05:58 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 148086219000 because target called exit() +Exiting @ tick 148086239000 because target called exit() diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt index 5c965f81e..33b349bfd 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,78 +1,82 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 419592 # Simulator instruction rate (inst/s) -host_mem_usage 369772 # Number of bytes of host memory used -host_seconds 217.30 # Real time elapsed on the host -host_tick_rate 681491064 # Simulator tick rate (ticks/s) +host_inst_rate 675901 # Simulator instruction rate (inst/s) +host_mem_usage 386672 # Number of bytes of host memory used +host_seconds 134.97 # Real time elapsed on the host +host_tick_rate 1097177206 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 91176087 # Number of instructions simulated +sim_insts 91226321 # Number of instructions simulated sim_seconds 0.148086 # Number of seconds simulated -sim_ticks 148086219000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 22564820 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14013.157105 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157105 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 21664622 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12614616000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.039894 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 900198 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 9914022000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.039894 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 900198 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 4738868 # number of WriteReq accesses(hits+misses) +sim_ticks 148086239000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 3887 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 22549408 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14013.157237 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157237 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 21649219 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 12614490000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.039921 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 900189 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 9913923000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.039921 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 900189 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 3887 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24109.399472 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 4692259 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 4688372 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 1263542000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.009835 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.009844 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 46609 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 1123715000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009835 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009844 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 46609 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 27.837649 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 27.825751 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 27303688 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 14657.853184 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 11657.853184 # average overall mshr miss latency -system.cpu.dcache.demand_hits 26356881 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 13878158000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.034677 # miss rate for demand accesses -system.cpu.dcache.demand_misses 946807 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 27284389 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 14657.859438 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency +system.cpu.dcache.demand_hits 26337591 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 13878032000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.034701 # miss rate for demand accesses +system.cpu.dcache.demand_misses 946798 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 11037737000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.034677 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 946807 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 11037638000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.034701 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 946798 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.871309 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 3568.882850 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 27303688 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 14657.853184 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 11657.853184 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.871228 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 3568.549501 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 27284389 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 14657.859438 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 26356881 # number of overall hits -system.cpu.dcache.overall_miss_latency 13878158000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.034677 # miss rate for overall accesses -system.cpu.dcache.overall_misses 946807 # number of overall misses +system.cpu.dcache.overall_hits 26337591 # number of overall hits +system.cpu.dcache.overall_miss_latency 13878032000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.034701 # miss rate for overall accesses +system.cpu.dcache.overall_misses 946798 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 11037737000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.034677 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 946807 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 11037638000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.034701 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 942711 # number of replacements -system.cpu.dcache.sampled_refs 946807 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 942702 # number of replacements +system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3568.882850 # Cycle average of tags in use -system.cpu.dcache.total_refs 26356881 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 54482100000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 942313 # number of writebacks +system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use +system.cpu.dcache.total_refs 26345365 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 54479156000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 942309 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -94,10 +98,10 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 107819118 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 107830780 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 54527.545910 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 107818519 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 107830181 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 32662000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 599 # number of ReadReq misses @@ -106,16 +110,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # ms system.cpu.icache.ReadReq_mshr_misses 599 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 179997.527546 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 180016.996661 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 107819118 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 107830780 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 54527.545910 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency -system.cpu.icache.demand_hits 107818519 # number of demand (read+write) hits +system.cpu.icache.demand_hits 107830181 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 32662000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses system.cpu.icache.demand_misses 599 # number of demand (read+write) misses @@ -126,13 +130,13 @@ system.cpu.icache.demand_mshr_misses 599 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.249185 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 510.330850 # Average occupied blocks per context -system.cpu.icache.overall_accesses 107819118 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.249187 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 510.335448 # Average occupied blocks per context +system.cpu.icache.overall_accesses 107830780 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 54527.545910 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 107818519 # number of overall hits +system.cpu.icache.overall_hits 107830181 # number of overall hits system.cpu.icache.overall_miss_latency 32662000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses system.cpu.icache.overall_misses 599 # number of overall misses @@ -145,8 +149,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 2 # number of replacements system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 510.330850 # Cycle average of tags in use -system.cpu.icache.total_refs 107818519 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 510.335448 # Cycle average of tags in use +system.cpu.icache.total_refs 107830181 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -181,84 +185,84 @@ system.cpu.l2cache.ReadExReq_misses 14548 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 581920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.312129 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 14548 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 900797 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 900788 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 899937 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits 899928 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 44720000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.000955 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 860 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 34400000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.000955 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 860 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 942313 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 942313 # number of Writeback hits +system.cpu.l2cache.Writeback_accesses 942309 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 942309 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 103.596349 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 103.595504 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 947406 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 947397 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 931998 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 931989 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 801216000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.016263 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate 0.016264 # miss rate for demand accesses system.cpu.l2cache.demand_misses 15408 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 616320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.016263 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.016264 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 15408 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.occ_%::0 0.009921 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.271910 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 325.103802 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 8909.939708 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 947406 # number of overall (read+write) accesses +system.cpu.l2cache.occ_%::1 0.271918 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 325.097811 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 8910.209882 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 947397 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 931998 # number of overall hits +system.cpu.l2cache.overall_hits 931989 # number of overall hits system.cpu.l2cache.overall_miss_latency 801216000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.016263 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate 0.016264 # miss rate for overall accesses system.cpu.l2cache.overall_misses 15408 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 616320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.016263 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.016264 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 15408 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 634 # number of replacements system.cpu.l2cache.sampled_refs 15392 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 9235.043509 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1594555 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 9235.307693 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1594542 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 32 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 296172438 # number of cpu cycles simulated +system.cpu.numCycles 296172478 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 296172438 # Number of busy cycles -system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_busy_cycles 296172478 # Number of busy cycles +system.cpu.num_conditional_control_insts 15112201 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_fp_insts 48 # number of float instructions system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 97900 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 91176087 # Number of instructions executed -system.cpu.num_int_alu_accesses 72483223 # Number of integer alu accesses -system.cpu.num_int_insts 72483223 # number of integer instructions -system.cpu.num_int_register_reads 257112085 # number of times the integer registers were read -system.cpu.num_int_register_writes 72558730 # number of times the integer registers were written -system.cpu.num_load_insts 22585492 # Number of load instructions -system.cpu.num_mem_refs 27330336 # number of memory refs +system.cpu.num_insts 91226321 # Number of instructions executed +system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses +system.cpu.num_int_insts 72525682 # number of integer instructions +system.cpu.num_int_register_reads 257193253 # number of times the integer registers were read +system.cpu.num_int_register_writes 72608963 # number of times the integer registers were written +system.cpu.num_load_insts 22573967 # Number of load instructions +system.cpu.num_mem_refs 27318811 # number of memory refs system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.workload.PROG:num_syscalls 442 # Number of system calls |