diff options
| author | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2011-04-19 18:45:23 -0700 |
| commit | 8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b (patch) | |
| tree | 8caf62f25cfd5047cd4f2c0f357267be9d79d7c4 /tests/long/10.mcf/ref | |
| parent | 63371c86648ed65a453a95aec80f326f15a9666d (diff) | |
| download | gem5-8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b.tar.xz | |
tests: update stats for name changes
Diffstat (limited to 'tests/long/10.mcf/ref')
22 files changed, 418 insertions, 414 deletions
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini index f89b48399..049d7897c 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -498,9 +498,9 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/arm/scratch/alisai01/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout index 9a7a71365..6a4d20d87 100755 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 17:54:33 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 12:49:23 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt index 365ff8ea3..9f9cc3407 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 190258 # Simulator instruction rate (inst/s) -host_mem_usage 391364 # Number of bytes of host memory used -host_seconds 479.61 # Real time elapsed on the host -host_tick_rate 93397782 # Simulator tick rate (ticks/s) +host_inst_rate 230945 # Simulator instruction rate (inst/s) +host_mem_usage 347768 # Number of bytes of host memory used +host_seconds 395.11 # Real time elapsed on the host +host_tick_rate 113371387 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91249905 # Number of instructions simulated sim_seconds 0.044795 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 1596208 # Nu system.cpu.BPredUnit.condPredicted 23792873 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 29586235 # Number of BP lookups system.cpu.BPredUnit.usedRAS 63032 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 18722470 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 671558 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 84101876 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.085142 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.487392 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 39810013 47.34% 47.34% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 21942954 26.09% 73.43% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 9544341 11.35% 84.77% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 7643789 9.09% 93.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2702545 3.21% 97.08% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 240327 0.29% 97.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 909211 1.08% 98.44% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 637138 0.76% 99.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 671558 0.80% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 84101876 # Number of insts commited each cycle -system.cpu.commit.COM:count 91262514 # Number of instructions committed -system.cpu.commit.COM:fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 56148 # Number of function calls committed. -system.cpu.commit.COM:int_insts 72533318 # Number of committed integer instructions. -system.cpu.commit.COM:loads 22575876 # Number of loads committed -system.cpu.commit.COM:membars 3888 # Number of memory barriers committed -system.cpu.commit.COM:refs 27322629 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 1599456 # The number of times a branch was mispredicted +system.cpu.commit.branches 18722470 # Number of branches committed +system.cpu.commit.bw_lim_events 671558 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 91262514 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 554406 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 37771309 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 84101876 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.085142 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.487392 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 39810013 47.34% 47.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 21942954 26.09% 73.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9544341 11.35% 84.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7643789 9.09% 93.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2702545 3.21% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 240327 0.29% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 909211 1.08% 98.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 637138 0.76% 99.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 671558 0.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 84101876 # Number of insts commited each cycle +system.cpu.commit.count 91262514 # Number of instructions committed +system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. +system.cpu.commit.function_calls 56148 # Number of function calls committed. +system.cpu.commit.int_insts 72533318 # Number of committed integer instructions. +system.cpu.commit.loads 22575876 # Number of loads committed +system.cpu.commit.membars 3888 # Number of memory barriers committed +system.cpu.commit.refs 27322629 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 91249905 # Number of Instructions Simulated system.cpu.committedInsts_total 91249905 # Number of Instructions Simulated system.cpu.cpi 0.981803 # CPI: Cycles Per Instruction @@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses 950233 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.852828 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 3493.184851 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.852828 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 29231190 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 8180.869220 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 3273.127173 # average overall mshr miss latency @@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse 3493.184851 # Cy system.cpu.dcache.total_refs 28069666 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 18896443000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 943153 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 17588781 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 9537 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4762375 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 139874563 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 32956661 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 32742845 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 5457924 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 30438 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 813588 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 17588781 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 9537 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 4762375 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 139874563 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 32956661 # Number of cycles decode is idle +system.cpu.decode.RunCycles 32742845 # Number of cycles decode is running +system.cpu.decode.SquashCycles 5457924 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 30438 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 813588 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -221,8 +221,8 @@ system.cpu.icache.demand_mshr_misses 674 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.277518 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 568.356083 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.277518 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 15336543 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35886.138614 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34397.626113 # average overall mshr miss latency @@ -245,21 +245,13 @@ system.cpu.icache.total_refs 15335735 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 29674 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 20951910 # Number of branches executed -system.cpu.iew.EXEC:nop 39919 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.157669 # Inst execution rate -system.cpu.iew.EXEC:refs 30258239 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 5196792 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 127150055 # num instructions consuming a value -system.cpu.iew.WB:count 102173263 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.489247 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 62207806 # num instructions producing a value -system.cpu.iew.WB:rate 1.140461 # insts written-back per cycle -system.cpu.iew.WB:sent 102563540 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 1809783 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 20951910 # Number of branches executed +system.cpu.iew.exec_nop 39919 # number of nop insts executed +system.cpu.iew.exec_rate 1.157669 # Inst execution rate +system.cpu.iew.exec_refs 30258239 # number of memory reference insts executed +system.cpu.iew.exec_stores 5196792 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 316819 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 31496278 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 689079 # Number of dispatched non-speculative instructions @@ -287,103 +279,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 1867594 # system.cpu.iew.memOrderViolationEvents 14224 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 282853 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 1526930 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 127150055 # num instructions consuming a value +system.cpu.iew.wb_count 102173263 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.489247 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 62207806 # num instructions producing a value +system.cpu.iew.wb_rate 1.140461 # insts written-back per cycle +system.cpu.iew.wb_sent 102563540 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 259728905 # number of integer regfile reads system.cpu.int_regfile_writes 80595212 # number of integer regfile writes system.cpu.ipc 1.018534 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.018534 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 74250134 70.21% 70.21% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 10532 0.01% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 1 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 27 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 46 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 5 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 70.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 26236363 24.81% 95.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 5264077 4.98% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 105761185 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 177153 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.001675 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 40759 23.01% 23.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 27 0.02% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 23.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 78448 44.28% 67.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 57919 32.69% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 89559799 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.180900 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.457109 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 38412400 42.89% 42.89% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 23501864 26.24% 69.13% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 14299372 15.97% 85.10% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 6452092 7.20% 92.30% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 2377583 2.65% 94.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2675567 2.99% 97.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1597319 1.78% 99.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 116596 0.13% 99.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 127006 0.14% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 89559799 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.180509 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74250134 70.21% 70.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10532 0.01% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 27 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 46 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26236363 24.81% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5264077 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 105761185 # Type of FU issued system.cpu.iq.fp_alu_accesses 110 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 216 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 99 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 196 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 177153 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001675 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 40759 23.01% 23.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.02% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 78448 44.28% 67.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 57919 32.69% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 105938228 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 301287282 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 102173164 # Number of integer instruction queue wakeup accesses @@ -395,6 +377,24 @@ system.cpu.iq.iqSquashedInstsExamined 37472339 # Nu system.cpu.iq.iqSquashedInstsIssued 28176 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 139525 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 69343981 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 89559799 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.180900 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.457109 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 38412400 42.89% 42.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23501864 26.24% 69.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 14299372 15.97% 85.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6452092 7.20% 92.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2377583 2.65% 94.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2675567 2.99% 97.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1597319 1.78% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 116596 0.13% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127006 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 89559799 # Number of insts issued each cycle +system.cpu.iq.rate 1.180509 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -468,10 +468,10 @@ system.cpu.l2cache.demand_mshr_misses 15537 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.012381 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.250026 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 405.690928 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 8192.856570 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.012381 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.250026 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 950905 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34233.211115 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31042.833237 # average overall mshr miss latency @@ -502,28 +502,28 @@ system.cpu.misc_regfile_writes 11602 # nu system.cpu.numCycles 89589473 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 2558009 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 71576967 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2891853 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 35560664 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1952065 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 58 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 350271207 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 135568411 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 105865304 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 30904016 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 5457924 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5891977 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 34288334 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 787 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 350270420 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 9187209 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 701223 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 13035103 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 702184 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 2558009 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 71576967 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 2891853 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 35560664 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 1952065 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 58 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 350271207 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 135568411 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 105865304 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 30904016 # Number of cycles rename is running +system.cpu.rename.SquashCycles 5457924 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 5891977 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 34288334 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 787 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 350270420 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 9187209 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 701223 # count of serializing insts renamed +system.cpu.rename.skidInsts 13035103 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 702184 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 212458407 # The number of ROB reads system.cpu.rob.rob_writes 263525841 # The number of ROB writes system.cpu.timesIdled 1433 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 442 # Number of system calls +system.cpu.workload.num_syscalls 442 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini index 2f887d410..a584d29ed 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -61,14 +61,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout index d4df9bd55..778a5635d 100755 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 17:54:34 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 12:50:38 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 4aa89302d..857cf86ba 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 950960 # Simulator instruction rate (inst/s) -host_mem_usage 379668 # Number of bytes of host memory used -host_seconds 95.96 # Real time elapsed on the host -host_tick_rate 565248287 # Simulator tick rate (ticks/s) +host_inst_rate 3623403 # Simulator instruction rate (inst/s) +host_mem_usage 338784 # Number of bytes of host memory used +host_seconds 25.18 # Real time elapsed on the host +host_tick_rate 2153732946 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91252969 # Number of instructions simulated sim_seconds 0.054241 # Number of seconds simulated @@ -71,6 +71,6 @@ system.cpu.num_int_register_writes 70993656 # nu system.cpu.num_load_insts 22573967 # Number of load instructions system.cpu.num_mem_refs 27318811 # number of memory refs system.cpu.num_store_insts 4744844 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 442 # Number of system calls +system.cpu.workload.num_syscalls 442 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini index 9fe66a752..b43580bea 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -164,14 +164,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout index 4622f4ee0..ce41a8bab 100755 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 17:54:34 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 12:51:14 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt index 389bae1e3..6b71bf251 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 492863 # Simulator instruction rate (inst/s) -host_mem_usage 387392 # Number of bytes of host memory used -host_seconds 185.09 # Real time elapsed on the host -host_tick_rate 800055292 # Simulator tick rate (ticks/s) +host_inst_rate 2007081 # Simulator instruction rate (inst/s) +host_mem_usage 346528 # Number of bytes of host memory used +host_seconds 45.45 # Real time elapsed on the host +host_tick_rate 3258049978 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91226321 # Number of instructions simulated sim_seconds 0.148086 # Number of seconds simulated @@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses 946798 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.871228 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 3568.549501 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.871228 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 27284389 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 14657.859438 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency @@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses 599 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.249187 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 510.335448 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.249187 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 107830780 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 54527.545910 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency @@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses 15408 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.009921 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.271918 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 325.097811 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 8910.209882 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.009921 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.271918 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 947397 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -264,6 +264,6 @@ system.cpu.num_int_register_writes 70993656 # nu system.cpu.num_load_insts 22573967 # Number of load instructions system.cpu.num_mem_refs 27318811 # number of memory refs system.cpu.num_store_insts 4744844 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 442 # Number of system calls +system.cpu.workload.num_syscalls 442 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout index a011c886e..a5435dfc1 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:13:30 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:14:01 -M5 executing on burrito +M5 compiled Apr 19 2011 12:19:46 +M5 started Apr 19 2011 12:20:18 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index 282686242..5f734ed46 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1159873 # Simulator instruction rate (inst/s) -host_mem_usage 351876 # Number of bytes of host memory used -host_seconds 210.23 # Real time elapsed on the host -host_tick_rate 581353978 # Simulator tick rate (ticks/s) +host_inst_rate 4484533 # Simulator instruction rate (inst/s) +host_mem_usage 329760 # Number of bytes of host memory used +host_seconds 54.37 # Real time elapsed on the host +host_tick_rate 2247743371 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated sim_seconds 0.122216 # Number of seconds simulated @@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 215451609 # nu system.cpu.num_load_insts 82803522 # Number of load instructions system.cpu.num_mem_refs 105711442 # number of memory refs system.cpu.num_store_insts 22907920 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 443 # Number of system calls +system.cpu.workload.num_syscalls 443 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index dd7acffe5..a1bafa0cb 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout index 280cd1a31..e8a8f1145 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:13:30 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:13:48 -M5 executing on burrito +M5 compiled Apr 19 2011 12:19:46 +M5 started Apr 19 2011 12:19:52 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 1b0d7fe21..3eb9bf1a6 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 483058 # Simulator instruction rate (inst/s) -host_mem_usage 359588 # Number of bytes of host memory used -host_seconds 504.77 # Real time elapsed on the host -host_tick_rate 718005180 # Simulator tick rate (ticks/s) +host_inst_rate 2305909 # Simulator instruction rate (inst/s) +host_mem_usage 337512 # Number of bytes of host memory used +host_seconds 105.74 # Real time elapsed on the host +host_tick_rate 3427441926 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated sim_seconds 0.362431 # Number of seconds simulated @@ -60,8 +60,8 @@ system.cpu.dcache.demand_mshr_misses 939567 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.870074 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 3563.824259 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.870074 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 14660.150899 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 11660.150899 # average overall mshr miss latency @@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses 882 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.354281 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 725.567632 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.354281 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55857.142857 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency @@ -183,10 +183,10 @@ system.cpu.l2cache.demand_mshr_misses 15648 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.011460 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.270424 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 375.506440 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 8861.245791 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.011460 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.270424 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -228,6 +228,6 @@ system.cpu.num_int_register_writes 215451608 # nu system.cpu.num_load_insts 82803522 # Number of load instructions system.cpu.num_mem_refs 105711442 # number of memory refs system.cpu.num_store_insts 22907920 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 443 # Number of system calls +system.cpu.workload.num_syscalls 443 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini index 1f2e75864..de48f92fd 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout index 2b45d7376..c33237447 100755 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2011 20:12:06 -M5 started Mar 18 2011 20:12:16 -M5 executing on zizzer +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:30:19 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt index 2d839c8d9..6bc8ba293 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 173311 # Simulator instruction rate (inst/s) -host_mem_usage 350460 # Number of bytes of host memory used -host_seconds 1605.16 # Real time elapsed on the host -host_tick_rate 50708988 # Simulator tick rate (ticks/s) +host_inst_rate 265187 # Simulator instruction rate (inst/s) +host_mem_usage 346300 # Number of bytes of host memory used +host_seconds 1049.04 # Real time elapsed on the host +host_tick_rate 77591071 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192519 # Number of instructions simulated sim_seconds 0.081396 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 2465320 # Nu system.cpu.BPredUnit.condPredicted 43504790 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 43504790 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 29309710 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 13548841 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 149131695 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.865415 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.481905 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 63516016 42.59% 42.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 27005826 18.11% 60.70% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 19486009 13.07% 73.77% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 13132636 8.81% 82.57% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 4245933 2.85% 85.42% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 3434891 2.30% 87.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 3062949 2.05% 89.78% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 1698594 1.14% 90.91% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 13548841 9.09% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 149131695 # Number of insts commited each cycle -system.cpu.commit.COM:count 278192519 # Number of instructions committed -system.cpu.commit.COM:fp_insts 40 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu.commit.COM:int_insts 278186227 # Number of committed integer instructions. -system.cpu.commit.COM:loads 90779388 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 122219139 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 2465329 # The number of times a branch was mispredicted +system.cpu.commit.branches 29309710 # Number of branches committed +system.cpu.commit.bw_lim_events 13548841 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 88842299 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 149131695 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.865415 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.481905 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 63516016 42.59% 42.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 27005826 18.11% 60.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 19486009 13.07% 73.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13132636 8.81% 82.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4245933 2.85% 85.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3434891 2.30% 87.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3062949 2.05% 89.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1698594 1.14% 90.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13548841 9.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149131695 # Number of insts commited each cycle +system.cpu.commit.count 278192519 # Number of instructions committed +system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. +system.cpu.commit.function_calls 0 # Number of function calls committed. +system.cpu.commit.int_insts 278186227 # Number of committed integer instructions. +system.cpu.commit.loads 90779388 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 122219139 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 278192519 # Number of Instructions Simulated system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated system.cpu.cpi 0.585179 # CPI: Cycles Per Instruction @@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses 2078004 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.994940 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4075.274681 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994940 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 94785588 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 7490.439865 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 3562.354617 # average overall mshr miss latency @@ -119,12 +119,12 @@ system.cpu.dcache.tagsinuse 4075.274681 # Cy system.cpu.dcache.total_refs 92329423 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 30396735000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 1448011 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 13645155 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 390459172 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 68124952 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 66154578 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 12492114 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 1207010 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 13645155 # Number of cycles decode is blocked +system.cpu.decode.DecodedInsts 390459172 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 68124952 # Number of cycles decode is idle +system.cpu.decode.RunCycles 66154578 # Number of cycles decode is running +system.cpu.decode.SquashCycles 12492114 # Number of cycles decode is squashing +system.cpu.decode.UnblockCycles 1207010 # Number of cycles decode is unblocking system.cpu.fetch.Branches 43504790 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 30855910 # Number of cache lines fetched system.cpu.fetch.Cycles 71218247 # Number of cycles fetch has run and was not squashing or blocked @@ -188,8 +188,8 @@ system.cpu.icache.demand_mshr_misses 1013 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.396500 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 812.031019 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.396500 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 30855910 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 36182.458888 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35209.772952 # average overall mshr miss latency @@ -212,21 +212,13 @@ system.cpu.icache.total_refs 30854633 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 1168640 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 32808514 # Number of branches executed -system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 2.009454 # Inst execution rate -system.cpu.iew.EXEC:refs 141715314 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 34352421 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 330470543 # num instructions consuming a value -system.cpu.iew.WB:count 324204287 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.735351 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 243011799 # num instructions producing a value -system.cpu.iew.WB:rate 1.991519 # insts written-back per cycle -system.cpu.iew.WB:sent 325408414 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 2866285 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 32808514 # Number of branches executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_rate 2.009454 # Inst execution rate +system.cpu.iew.exec_refs 141715314 # number of memory reference insts executed +system.cpu.iew.exec_stores 34352421 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 739357 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 121527888 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions @@ -254,103 +246,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 8203432 # system.cpu.iew.memOrderViolationEvents 237293 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 582972 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 2283313 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 330470543 # num instructions consuming a value +system.cpu.iew.wb_count 324204287 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.735351 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 243011799 # num instructions producing a value +system.cpu.iew.wb_rate 1.991519 # insts written-back per cycle +system.cpu.iew.wb_sent 325408414 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 572686347 # number of integer regfile reads system.cpu.int_regfile_writes 291536884 # number of integer regfile writes system.cpu.ipc 1.708879 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.708879 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16703 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 188329198 56.76% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 16 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 108641887 32.74% 89.51% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 34821337 10.49% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 331809141 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1744992 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.005259 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 20475 1.17% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 1576903 90.37% 91.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 147614 8.46% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 161623809 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 2.052972 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.792191 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 44438080 27.49% 27.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 26560474 16.43% 43.93% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 27560184 17.05% 60.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 26726118 16.54% 77.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 19530475 12.08% 89.60% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 11104171 6.87% 96.47% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 3863575 2.39% 98.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 1600116 0.99% 99.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 240616 0.15% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 161623809 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 2.038234 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 16703 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 188329198 56.76% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 16 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 108641887 32.74% 89.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34821337 10.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 331809141 # Type of FU issued system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 208 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 80 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 238 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1744992 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005259 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 20475 1.17% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1576903 90.37% 91.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 147614 8.46% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 333537329 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 827162429 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 324204207 # Number of integer instruction queue wakeup accesses @@ -362,6 +344,24 @@ system.cpu.iq.iqSquashedInstsExamined 88592670 # Nu system.cpu.iq.iqSquashedInstsIssued 175554 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 124945161 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 161623809 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.052972 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.792191 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 44438080 27.49% 27.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 26560474 16.43% 43.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 27560184 17.05% 60.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 26726118 16.54% 77.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19530475 12.08% 89.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 11104171 6.87% 96.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3863575 2.39% 98.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1600116 0.99% 99.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 240616 0.15% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 161623809 # Number of insts issued each cycle +system.cpu.iq.rate 2.038234 # Inst issue rate system.cpu.l2cache.ReadExReq_accesses 106011 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 34192.017786 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31115.893095 # average ReadExReq mshr miss latency @@ -413,10 +413,10 @@ system.cpu.l2cache.demand_mshr_misses 76519 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.196368 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.354446 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 6434.571377 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 11614.477696 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.196368 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.354446 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 2079015 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34202.596741 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31074.223395 # average overall mshr miss latency @@ -446,28 +446,28 @@ system.cpu.misc_regfile_reads 211169577 # nu system.cpu.numCycles 162792449 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 3023364 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 248344192 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 130274 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 72054036 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 9710787 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 12 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 941229334 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 383108308 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 343773743 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 63044913 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 12492114 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 11002939 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 95429551 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 586 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 941228748 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 6443 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 468 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 25868384 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 462 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 3023364 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 130274 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 72054036 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 9710787 # Number of times rename has blocked due to LSQ full +system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 941229334 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 383108308 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 343773743 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 63044913 # Number of cycles rename is running +system.cpu.rename.SquashCycles 12492114 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 11002939 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 95429551 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 586 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 941228748 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 6443 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 468 # count of serializing insts renamed +system.cpu.rename.skidInsts 25868384 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 462 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 502617672 # The number of ROB reads system.cpu.rob.rob_writes 746575877 # The number of ROB writes system.cpu.timesIdled 40062 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 444 # Number of system calls +system.cpu.workload.num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout index 2aa2852be..0d61b002c 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 00:58:32 -M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip -M5 started Feb 8 2011 00:58:34 -M5 executing on burrito +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:39:34 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt index aacdb2309..ed3183ec3 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1568972 # Simulator instruction rate (inst/s) -host_mem_usage 358500 # Number of bytes of host memory used -host_seconds 177.31 # Real time elapsed on the host -host_tick_rate 952856596 # Simulator tick rate (ticks/s) +host_inst_rate 3107267 # Simulator instruction rate (inst/s) +host_mem_usage 337076 # Number of bytes of host memory used +host_seconds 89.53 # Real time elapsed on the host +host_tick_rate 1887081425 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192520 # Number of instructions simulated sim_seconds 0.168950 # Number of seconds simulated @@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 248344166 # nu system.cpu.num_load_insts 90779388 # Number of load instructions system.cpu.num_mem_refs 122219139 # number of memory refs system.cpu.num_store_insts 31439751 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 444 # Number of system calls +system.cpu.workload.num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini index 12f3ad44d..2184f1531 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index 56b5fe9df..1d6e35c6c 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 00:58:32 -M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip -M5 started Feb 8 2011 00:58:34 -M5 executing on burrito +M5 compiled Apr 19 2011 12:22:33 +M5 started Apr 19 2011 12:41:14 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index e90dea7b7..e994cf670 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1018906 # Simulator instruction rate (inst/s) -host_mem_usage 366224 # Number of bytes of host memory used -host_seconds 273.03 # Real time elapsed on the host -host_tick_rate 1355197592 # Simulator tick rate (ticks/s) +host_inst_rate 1776708 # Simulator instruction rate (inst/s) +host_mem_usage 344820 # Number of bytes of host memory used +host_seconds 156.58 # Real time elapsed on the host +host_tick_rate 2363113199 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192520 # Number of instructions simulated sim_seconds 0.370011 # Number of seconds simulated @@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 2066829 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995279 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995279 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 808 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.325289 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -173,10 +173,10 @@ system.cpu.l2cache.demand_mshr_misses 76575 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.199945 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.368128 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.199945 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.368128 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -218,6 +218,6 @@ system.cpu.num_int_register_writes 248344166 # nu system.cpu.num_load_insts 90779388 # Number of load instructions system.cpu.num_mem_refs 122219139 # number of memory refs system.cpu.num_store_insts 31439751 # Number of store instructions -system.cpu.workload.PROG:num_syscalls 444 # Number of system calls +system.cpu.workload.num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- |