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authorLisa Hsu <Lisa.Hsu@amd.com>2010-02-25 10:08:41 -0800
committerLisa Hsu <Lisa.Hsu@amd.com>2010-02-25 10:08:41 -0800
commitee20a7c0bddf1f2a1913ddb176910bdce4c13b9c (patch)
tree93b9bd8be890468c550b85eae4b467285b4d6811 /tests/long/10.mcf/ref
parent7f3cd9a9fd636c1e48dcec20de3f6c14214d0ce4 (diff)
downloadgem5-ee20a7c0bddf1f2a1913ddb176910bdce4c13b9c.tar.xz
stats: update stats for the changes I pushed re: shared cache occupancy
Diffstat (limited to 'tests/long/10.mcf/ref')
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini4
-rwxr-xr-xtests/long/10.mcf/ref/sparc/linux/simple-atomic/simout8
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt8
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini10
-rwxr-xr-xtests/long/10.mcf/ref/sparc/linux/simple-timing/simout8
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt16
-rw-r--r--tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini6
-rwxr-xr-xtests/long/10.mcf/ref/x86/linux/simple-atomic/simout10
-rw-r--r--tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt8
-rw-r--r--tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini7
-rwxr-xr-xtests/long/10.mcf/ref/x86/linux/simple-timing/simout8
-rw-r--r--tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt16
12 files changed, 64 insertions, 45 deletions
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index 93528e180..d56440ca5 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -57,9 +57,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
index 529f20a79..6c4e0d9c5 100755
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 21 2009 18:04:32
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 18:06:05
-M5 executing on zizzer
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:27:41
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
index ce9766cbc..2eefb0962 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2430508 # Simulator instruction rate (inst/s)
-host_mem_usage 329972 # Number of bytes of host memory used
-host_seconds 100.32 # Real time elapsed on the host
-host_tick_rate 1218223693 # Simulator tick rate (ticks/s)
+host_inst_rate 1458389 # Simulator instruction rate (inst/s)
+host_mem_usage 317928 # Number of bytes of host memory used
+host_seconds 167.20 # Real time elapsed on the host
+host_tick_rate 730976871 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated
sim_seconds 0.122216 # Number of seconds simulated
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
index 676b1ef8d..b6cfae717 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -45,7 +45,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -80,7 +80,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -115,7 +115,7 @@ hash_delay=1
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
@@ -157,9 +157,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
index 431d9905a..80c9b27b1 100755
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:47
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:30:43
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:30:29
+M5 executing on SC2B0619
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 803a77546..5683e9007 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1809872 # Simulator instruction rate (inst/s)
-host_mem_usage 339332 # Number of bytes of host memory used
-host_seconds 134.73 # Real time elapsed on the host
-host_tick_rate 2719868473 # Simulator tick rate (ticks/s)
+host_inst_rate 794629 # Simulator instruction rate (inst/s)
+host_mem_usage 325576 # Number of bytes of host memory used
+host_seconds 306.85 # Real time elapsed on the host
+host_tick_rate 1194166006 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated
sim_seconds 0.366435 # Number of seconds simulated
@@ -60,6 +60,8 @@ system.cpu.dcache.demand_mshr_misses 987820 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.871490 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 3569.622607 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 18046.382944 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency
@@ -113,6 +115,8 @@ system.cpu.icache.demand_mshr_misses 882 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.354611 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 726.242454 # Average occupied blocks per context
system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency
@@ -187,6 +191,10 @@ system.cpu.l2cache.demand_mshr_misses 47800 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.010976 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.262444 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 359.659901 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 8599.756547 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
index 7c74336b4..662e9141e 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -52,14 +52,14 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
index faf614c2c..f9e963c82 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 17 2009 20:29:57
-M5 revision 84f7bdc43a4f 6605 default qtip tip x86fsdate.patch
-M5 started Aug 17 2009 20:30:53
-M5 executing on tater
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:50:08
+M5 executing on SC2B0619
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index 16f0b4a6b..0cb316cbf 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 635652 # Simulator instruction rate (inst/s)
-host_mem_usage 347576 # Number of bytes of host memory used
-host_seconds 424.28 # Real time elapsed on the host
-host_tick_rate 388188748 # Simulator tick rate (ticks/s)
+host_inst_rate 1130966 # Simulator instruction rate (inst/s)
+host_mem_usage 323116 # Number of bytes of host memory used
+host_seconds 238.47 # Real time elapsed on the host
+host_tick_rate 690673696 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 269695959 # Number of instructions simulated
sim_seconds 0.164702 # Number of seconds simulated
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
index c90ba3ccf..14d594ef3 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -45,6 +45,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -79,6 +80,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -113,6 +115,7 @@ hash_delay=1
latency=10000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
@@ -154,9 +157,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
index 035c663f2..3d3eaa281 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 8 2009 16:16:58
-M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff
-M5 started Nov 8 2009 16:34:05
-M5 executing on maize
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:52:35
+M5 executing on SC2B0619
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
index b582ff405..5338d200d 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 839358 # Simulator instruction rate (inst/s)
-host_mem_usage 328912 # Number of bytes of host memory used
-host_seconds 321.31 # Real time elapsed on the host
-host_tick_rate 1189158712 # Simulator tick rate (ticks/s)
+host_inst_rate 855655 # Simulator instruction rate (inst/s)
+host_mem_usage 331116 # Number of bytes of host memory used
+host_seconds 315.19 # Real time elapsed on the host
+host_tick_rate 1212247082 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 269695959 # Number of instructions simulated
sim_seconds 0.382091 # Number of seconds simulated
@@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 2195642 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.995395 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4077.137530 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 122219193 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 20188.783508 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 17188.783508 # average overall mshr miss latency
@@ -103,6 +105,8 @@ system.cpu.icache.demand_mshr_misses 808 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.325918 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 667.480800 # Average occupied blocks per context
system.cpu.icache.overall_accesses 217696172 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
@@ -177,6 +181,10 @@ system.cpu.l2cache.demand_mshr_misses 195509 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.198854 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.350512 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 6516.062046 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 11485.589337 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 2067619 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000.158560 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency