diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:13 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:13 -0800 |
| commit | 0851580aada37c8e1b1d2b695100fbcfaf4e0946 (patch) | |
| tree | 96eea53d6309ddb9f4bfac61767e53bfcdb44037 /tests/long/10.mcf/ref | |
| parent | 1b64bfa933745294667158d0ce22180780b2a22e (diff) | |
| download | gem5-0851580aada37c8e1b1d2b695100fbcfaf4e0946.tar.xz | |
Stats: Re update stats.
Diffstat (limited to 'tests/long/10.mcf/ref')
25 files changed, 305 insertions, 94 deletions
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini index 67f0de766..9285fee06 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -484,9 +493,9 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout index 43dc1d1fc..591032c8f 100755 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 11 2011 18:16:01 -M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip -M5 started Jan 12 2011 03:03:04 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:58:27 +M5 executing on burrito command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt index 674012633..390072636 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 109166 # Simulator instruction rate (inst/s) -host_mem_usage 384348 # Number of bytes of host memory used -host_seconds 835.45 # Real time elapsed on the host -host_tick_rate 67095197 # Simulator tick rate (ticks/s) +host_inst_rate 65288 # Simulator instruction rate (inst/s) +host_mem_usage 370872 # Number of bytes of host memory used +host_seconds 1396.92 # Real time elapsed on the host +host_tick_rate 40127232 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91202735 # Number of instructions simulated sim_seconds 0.056055 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 109380669 # Number of insts commited each cycle system.cpu.commit.COM:count 91202735 # Number of instructions committed +system.cpu.commit.COM:fp_insts 48 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 72483223 # Number of committed integer instructions. system.cpu.commit.COM:loads 22585492 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 27330336 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 112077802 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 75 # number of floating regfile reads +system.cpu.fp_regfile_writes 47 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 12683523 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 36326.451613 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34504.457652 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 788441 # system.cpu.iew.memOrderViolationEvents 1330 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 76117 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 1979748 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 246289928 # number of integer regfile reads +system.cpu.int_regfile_writes 76222702 # number of integer regfile writes system.cpu.ipc 0.813516 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.813516 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 112077802 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.888775 # Inst issue rate +system.cpu.iq.fp_alu_accesses 74 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 144 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 100131195 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 311849254 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 96607706 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 112840034 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 102487226 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 99639939 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 553822 # Number of non-speculative instructions added to the IQ @@ -463,7 +478,11 @@ system.cpu.memDep0.conflictingLoads 436025 # Nu system.cpu.memDep0.conflictingStores 249497 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 24681131 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 5533285 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 157552604 # number of misc regfile reads +system.cpu.misc_regfile_writes 1603309 # number of misc regfile writes system.cpu.numCycles 112109302 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 294826 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 72061910 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 4906 # Number of times rename has blocked due to IQ full @@ -476,10 +495,14 @@ system.cpu.rename.RENAME:RunCycles 72730212 # Nu system.cpu.rename.RENAME:SquashCycles 2697133 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 723330 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 11862848 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 474 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 277458644 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 5701177 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 592742 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 1065555 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 576556 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 212048427 # The number of ROB reads +system.cpu.rob.rob_writes 208775903 # The number of ROB writes system.cpu.timesIdled 1292 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 442 # Number of system calls diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini index bfff6943f..a584d29ed 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -52,14 +61,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout index d622d0388..34dd3ff53 100755 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:40:32 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:24 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 9bb34897d..0d4b35c47 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2560594 # Simulator instruction rate (inst/s) -host_mem_usage 386656 # Number of bytes of host memory used -host_seconds 35.62 # Real time elapsed on the host -host_tick_rate 1522136495 # Simulator tick rate (ticks/s) +host_inst_rate 937948 # Simulator instruction rate (inst/s) +host_mem_usage 362060 # Number of bytes of host memory used +host_seconds 97.24 # Real time elapsed on the host +host_tick_rate 557562760 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91202735 # Number of instructions simulated sim_seconds 0.054216 # Number of seconds simulated @@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 108431099 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 108431099 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses +system.cpu.num_fp_insts 48 # number of float instructions +system.cpu.num_fp_register_reads 54 # number of times the floating registers were read +system.cpu.num_fp_register_writes 30 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 91202735 # Number of instructions executed -system.cpu.num_refs 27330336 # Number of memory references +system.cpu.num_int_alu_accesses 72483223 # Number of integer alu accesses +system.cpu.num_int_insts 72483223 # number of integer instructions +system.cpu.num_int_register_reads 234567931 # number of times the integer registers were read +system.cpu.num_int_register_writes 72546720 # number of times the integer registers were written +system.cpu.num_load_insts 22585492 # Number of load instructions +system.cpu.num_mem_refs 27330336 # number of memory refs +system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.workload.PROG:num_syscalls 442 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini index d78abde62..d7d6a4868 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,14 +161,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr index eabe42249..c1c8fcec5 100755 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simerr @@ -1,3 +1,7 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout index c45082899..b290f1d74 100755 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:41:18 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt index bb2ffd900..5c965f81e 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 587679 # Simulator instruction rate (inst/s) -host_mem_usage 394372 # Number of bytes of host memory used -host_seconds 155.15 # Real time elapsed on the host -host_tick_rate 954493550 # Simulator tick rate (ticks/s) +host_inst_rate 419592 # Simulator instruction rate (inst/s) +host_mem_usage 369772 # Number of bytes of host memory used +host_seconds 217.30 # Real time elapsed on the host +host_tick_rate 681491064 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91176087 # Number of instructions simulated sim_seconds 0.148086 # Number of seconds simulated @@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 32 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 296172438 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 296172438 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses +system.cpu.num_fp_insts 48 # number of float instructions +system.cpu.num_fp_register_reads 54 # number of times the floating registers were read +system.cpu.num_fp_register_writes 30 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 91176087 # Number of instructions executed -system.cpu.num_refs 27330336 # Number of memory references +system.cpu.num_int_alu_accesses 72483223 # Number of integer alu accesses +system.cpu.num_int_insts 72483223 # number of integer instructions +system.cpu.num_int_register_reads 257112085 # number of times the integer registers were read +system.cpu.num_int_register_writes 72558730 # number of times the integer registers were written +system.cpu.num_load_insts 22585492 # Number of load instructions +system.cpu.num_mem_refs 27330336 # number of memory refs +system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.workload.PROG:num_syscalls 442 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini index 06fed5d59..164664341 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,9 +66,9 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/mcf +executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf gid=100 -input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout index 6c4e0d9c5..a011c886e 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:27:41 -M5 executing on SC2B0619 +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:14:01 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index 2eefb0962..282686242 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1458389 # Simulator instruction rate (inst/s) -host_mem_usage 317928 # Number of bytes of host memory used -host_seconds 167.20 # Real time elapsed on the host -host_tick_rate 730976871 # Simulator tick rate (ticks/s) +host_inst_rate 1159873 # Simulator instruction rate (inst/s) +host_mem_usage 351876 # Number of bytes of host memory used +host_seconds 210.23 # Real time elapsed on the host +host_tick_rate 581353978 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated sim_seconds 0.122216 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 122215830000 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 244431661 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 244431661 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses +system.cpu.num_fp_insts 11630 # number of float instructions +system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read +system.cpu.num_fp_register_writes 90 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 243835278 # Number of instructions executed -system.cpu.num_refs 105711442 # Number of memory references +system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses +system.cpu.num_int_insts 194726506 # number of integer instructions +system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read +system.cpu.num_int_register_writes 215451609 # number of times the integer registers were written +system.cpu.num_load_insts 82803522 # Number of load instructions +system.cpu.num_mem_refs 105711442 # number of memory refs +system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.workload.PROG:num_syscalls 443 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index e885b2b99..dd7acffe5 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,14 +161,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing +cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/mcf +executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf gid=100 -input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout index b2d326b66..280cd1a31 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 16:31:43 -M5 executing on phenom -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:48 +M5 executing on burrito +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt index f56720371..1b0d7fe21 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1229097 # Simulator instruction rate (inst/s) -host_mem_usage 329428 # Number of bytes of host memory used -host_seconds 198.39 # Real time elapsed on the host -host_tick_rate 1826897848 # Simulator tick rate (ticks/s) +host_inst_rate 483058 # Simulator instruction rate (inst/s) +host_mem_usage 359588 # Number of bytes of host memory used +host_seconds 504.77 # Real time elapsed on the host +host_tick_rate 718005180 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated sim_seconds 0.362431 # Number of seconds simulated @@ -210,8 +210,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 40 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 724861774 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 724861774 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses +system.cpu.num_fp_insts 11630 # number of float instructions +system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read +system.cpu.num_fp_register_writes 90 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 243835278 # Number of instructions executed -system.cpu.num_refs 105711442 # Number of memory references +system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses +system.cpu.num_int_insts 194726506 # number of integer instructions +system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read +system.cpu.num_int_register_writes 215451608 # number of times the integer registers were written +system.cpu.num_load_insts 82803522 # Number of load instructions +system.cpu.num_mem_refs 105711442 # number of memory refs +system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.workload.PROG:num_syscalls 443 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini index 60f53a64a..8e006cde5 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -481,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing +cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout index fde487a8e..bf0cc96de 100755 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 16:34:44 -M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch -M5 started Jan 31 2011 16:34:46 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:24 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt index 8ba88fe5a..3db6ff161 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 76828 # Simulator instruction rate (inst/s) -host_mem_usage 366252 # Number of bytes of host memory used -host_seconds 3621.00 # Real time elapsed on the host -host_tick_rate 47136339 # Simulator tick rate (ticks/s) +host_inst_rate 83481 # Simulator instruction rate (inst/s) +host_mem_usage 366872 # Number of bytes of host memory used +host_seconds 3332.41 # Real time elapsed on the host +host_tick_rate 51218385 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192519 # Number of instructions simulated sim_seconds 0.170681 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 321793097 # Number of insts commited each cycle system.cpu.commit.COM:count 278192519 # Number of instructions committed +system.cpu.commit.COM:fp_insts 40 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 278186227 # Number of committed integer instructions. system.cpu.commit.COM:loads 90779388 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 122219139 # Number of memory references committed @@ -150,6 +153,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 341246945 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 44 # number of floating regfile reads +system.cpu.fp_regfile_writes 31 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 39245397 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 37208.490566 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35316.192560 # average ReadReq mshr miss latency @@ -249,6 +254,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 9599437 # system.cpu.iew.memOrderViolationEvents 5520980 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 16897 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 5373424 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 754340794 # number of integer regfile reads +system.cpu.int_regfile_writes 286169707 # number of integer regfile writes system.cpu.ipc 0.814950 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.814950 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16700 0.01% 0.01% # Type of FU issued @@ -340,6 +347,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 341246945 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.976510 # Inst issue rate +system.cpu.iq.fp_alu_accesses 55 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 110 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 49 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 110 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 333424039 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1008030271 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 317781500 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 504991584 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 389592403 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 333342642 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 455 # Number of non-speculative instructions added to the IQ @@ -419,7 +434,10 @@ system.cpu.memDep0.conflictingLoads 22358679 # Nu system.cpu.memDep0.conflictingStores 3757180 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 131280417 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 41039188 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 204301939 # number of misc regfile reads system.cpu.numCycles 341361263 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 486743 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 248344192 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 12249 # Number of times rename has blocked due to IQ full @@ -432,10 +450,14 @@ system.cpu.rename.RENAME:RunCycles 222275258 # Nu system.cpu.rename.RENAME:SquashCycles 19453848 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 514692 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 129004058 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 291 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 1292599352 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 5287 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 454 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 779091 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 452 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 708961934 # The number of ROB reads +system.cpu.rob.rob_writes 799263493 # The number of ROB writes system.cpu.timesIdled 5627 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 444 # Number of system calls diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini index f7e610d03..f21f47f4d 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -54,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic +cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout index dfdd5bece..e76d60819 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:12 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 82026f43b..bcab65c40 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 938582 # Simulator instruction rate (inst/s) -host_mem_usage 354336 # Number of bytes of host memory used -host_seconds 296.40 # Real time elapsed on the host -host_tick_rate 570013222 # Simulator tick rate (ticks/s) +host_inst_rate 722489 # Simulator instruction rate (inst/s) +host_mem_usage 358012 # Number of bytes of host memory used +host_seconds 385.05 # Real time elapsed on the host +host_tick_rate 438776725 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192520 # Number of instructions simulated sim_seconds 0.168950 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 168950072000 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 337900145 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 337900145 # Number of busy cycles +system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses +system.cpu.num_fp_insts 40 # number of float instructions +system.cpu.num_fp_register_reads 40 # number of times the floating registers were read +system.cpu.num_fp_register_writes 26 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 278192520 # Number of instructions executed -system.cpu.num_refs 122219139 # Number of memory references +system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses +system.cpu.num_int_insts 278186228 # number of integer instructions +system.cpu.num_int_register_reads 855210512 # number of times the integer registers were read +system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written +system.cpu.num_load_insts 90779388 # Number of load instructions +system.cpu.num_mem_refs 122219139 # number of memory refs +system.cpu.num_store_insts 31439751 # Number of store instructions system.cpu.workload.PROG:num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini index 217d838ce..12f3ad44d 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -154,7 +161,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index 68ecd8732..0b92276cc 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:12 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index 7c84c26e1..cf6f03e98 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 734335 # Simulator instruction rate (inst/s) -host_mem_usage 362052 # Number of bytes of host memory used -host_seconds 378.84 # Real time elapsed on the host -host_tick_rate 976703915 # Simulator tick rate (ticks/s) +host_inst_rate 424375 # Simulator instruction rate (inst/s) +host_mem_usage 365728 # Number of bytes of host memory used +host_seconds 655.54 # Real time elapsed on the host +host_tick_rate 564440982 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192520 # Number of instructions simulated sim_seconds 0.370011 # Number of seconds simulated @@ -200,8 +200,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 29460 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 740021680 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 740021680 # Number of busy cycles +system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses +system.cpu.num_fp_insts 40 # number of float instructions +system.cpu.num_fp_register_reads 40 # number of times the floating registers were read +system.cpu.num_fp_register_writes 26 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 278192520 # Number of instructions executed -system.cpu.num_refs 122219139 # Number of memory references +system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses +system.cpu.num_int_insts 278186228 # number of integer instructions +system.cpu.num_int_register_reads 855210512 # number of times the integer registers were read +system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written +system.cpu.num_load_insts 90779388 # Number of load instructions +system.cpu.num_mem_refs 122219139 # number of memory refs +system.cpu.num_store_insts 31439751 # Number of store instructions system.cpu.workload.PROG:num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- |