Make default PhysicalMemory latency slightly more realistic.

Also update stats to reflect change.

4 files changed, 71 insertions, 71 deletions

diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
index a9975c5c8..0493cbfab 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
 [system.physmem]
 type=PhysicalMemory
 file=
-latency=1
+latency=30000
 latency_var=0
 null=false
 range=0:268435455
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
index 797c83359..eb056d4cc 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,41 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2198270                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 346304                       # Number of bytes of host memory used
-host_seconds                                   110.92                       # Real time elapsed on the host
-host_tick_rate                             3278529226                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1384402                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 334744                       # Number of bytes of host memory used
+host_seconds                                   176.13                       # Real time elapsed on the host
+host_tick_rate                             2080531769                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   243835278                       # Number of instructions simulated
-sim_seconds                                  0.363660                       # Number of seconds simulated
-sim_ticks                                363659868000                       # Number of ticks simulated
+sim_seconds                                  0.366446                       # Number of seconds simulated
+sim_ticks                                366445521000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           82220434                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14002.999360                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11002.999360                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 14009.690242                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.690242                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               81327577                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    12502676000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency    12508650000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.010859                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses               892857                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   9824105000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   9830079000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.010859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses          892857                       # number of ReadReq MSHR misses
 system.cpu.dcache.SwapReq_accesses               3886                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency        27000                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency        24000                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency        56000                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency        53000                       # average SwapReq mshr miss latency
 system.cpu.dcache.SwapReq_hits                   3878                       # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency         216000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency         448000                       # number of SwapReq miss cycles
 system.cpu.dcache.SwapReq_miss_rate          0.002059                       # miss rate for SwapReq accesses
 system.cpu.dcache.SwapReq_misses                    8                       # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency       192000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency       424000                       # number of SwapReq MSHR miss cycles
 system.cpu.dcache.SwapReq_mshr_miss_rate     0.002059                       # mshr miss rate for SwapReq accesses
 system.cpu.dcache.SwapReq_mshr_misses               8                       # number of SwapReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          22901951                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency        27000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        24000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits              22806988                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    2564001000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    5317928000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.004147                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses               94963                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   2279112000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   5033039000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.004147                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses          94963                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           105122385                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 15252.451864                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 12252.451864                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 18046.382944                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 15046.382944                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits               104134565                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     15066677000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency     17826578000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.009397                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                987820                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  12103217000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  14863118000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.009397                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses           987820                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses          105122385                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 15252.451864                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 12252.451864                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 18046.382944                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 15046.382944                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits              104134565                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    15066677000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency    17826578000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.009397                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses               987820                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  12103217000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  14863118000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.009397                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses          987820                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                 935475                       # number of replacements
 system.cpu.dcache.sampled_refs                 939571                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               3566.422282                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               3569.547350                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                104186700                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle           134205827000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle           134389803000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                    94875                       # number of writebacks
 system.cpu.icache.ReadReq_accesses          244431627                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 26970.521542                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 23970.521542                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 55904.761905                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits              244430745                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       23788000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency       49308000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  882                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency     21142000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     46662000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             882                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses           244431627                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 26970.521542                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 23970.521542                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 55904.761905                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52904.761905                       # average overall mshr miss latency
 system.cpu.icache.demand_hits               244430745                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        23788000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency        49308000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000004                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   882                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     21142000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     46662000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses              882                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses          244431627                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 26970.521542                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 23970.521542                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 55904.761905                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits              244430745                       # number of overall hits
-system.cpu.icache.overall_miss_latency       23788000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency       49308000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  882                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     21142000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     46662000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000004                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses             882                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -148,37 +148,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                     25                       # number of replacements
 system.cpu.icache.sampled_refs                    882                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                725.877742                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                726.233997                       # Cycle average of tags in use
 system.cpu.icache.total_refs                244430745                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.l2cache.ReadExReq_accesses           46714                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        23000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        11000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency   1074422000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency   2429128000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_misses             46714                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    513854000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1868560000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses        46714                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses            893739                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        23000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        11000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                892653                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency      24978000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency      56472000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.001215                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses                1086                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     11946000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency     43440000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.001215                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses           1086                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_accesses          48257                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        23000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        11000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency   1109911000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency   2509364000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_misses            48257                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency    530827000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency   1930280000                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_misses        48257                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.Writeback_accesses           94875                       # number of Writeback accesses(hits+misses)
@@ -192,29 +192,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses             940453                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        23000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                 892653                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     1099400000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency     2485600000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.050827                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                47800                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    525800000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   1912000000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_rate     0.050827                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses           47800                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses            940453                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        23000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                892653                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    1099400000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency    2485600000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.050827                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses               47800                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    525800000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   1912000000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_rate     0.050827                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses          47800                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements                   891                       # number of replacements
 system.cpu.l2cache.sampled_refs                 15559                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              8943.216339                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              8958.603097                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  802210                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                      41                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        727319736                       # number of cpu cycles simulated
+system.cpu.numCycles                        732891042                       # number of cpu cycles simulated
 system.cpu.num_insts                        243835278                       # Number of instructions executed
 system.cpu.num_refs                         105711442                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             443                       # Number of system calls
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr
index c59920875..320065be7 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr
@@ -1,2 +1,2 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7004
+0: system.remote_gdb.listener: listening for remote gdb on port 7001
 warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
index 66cc737ad..1d6b63175 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jul 23 2008 16:00:51
-M5 started Wed Jul 23 16:00:53 2008
-M5 executing on blue
-M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf
-M5 commit date Wed Jul 23 15:35:08 2008 -0700
+M5 compiled Aug  2 2008 17:21:13
+M5 started Sat Aug  2 17:25:03 2008
+M5 executing on zizzer
+M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
+M5 commit date Thu Jul 31 08:01:38 2008 -0700
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 
@@ -28,4 +28,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 363659868000 because target called exit()
+Exiting @ tick 366445521000 because target called exit()