update all the regresstion tests for release

--HG--
extra : convert_revision : 47e420b5b27e196a6e7a6424540923623bb3c4d2

8 files changed, 77 insertions, 77 deletions

diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index 368feb9a9..9b8d69888 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -48,6 +48,7 @@ uid=100
 
 [system.membus]
 type=Bus
+block_size=64
 bus_id=0
 clock=1000
 responder_set=false
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out
index 24228b2bd..8a5c9fd62 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out
@@ -20,6 +20,7 @@ bus_id=0
 clock=1000
 width=64
 responder_set=false
+block_size=64
 
 [system.cpu.workload]
 type=LiveProcess
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt
index 7e603ae8c..530572b5d 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 658093                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 149896                       # Number of bytes of host memory used
-host_seconds                                  2613.00                       # Real time elapsed on the host
-host_tick_rate                              329046277                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 686638                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 149820                       # Number of bytes of host memory used
+host_seconds                                  2504.37                       # Real time elapsed on the host
+host_tick_rate                              343319148                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1719594534                       # Number of instructions simulated
 sim_seconds                                  0.859797                       # Number of seconds simulated
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout
index f52ad5eac..bd861b307 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout
@@ -25,8 +25,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 27 2007 14:35:32
-M5 started Fri Apr 27 15:11:49 2007
+M5 compiled May 15 2007 13:02:31
+M5 started Tue May 15 14:23:47 2007
 M5 executing on zizzer.eecs.umich.edu
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
index 6e102e359..9beb527ea 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -36,8 +36,7 @@ block_size=64
 compressed_bus=false
 compression_latency=0
 hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
 lifo=false
 max_miss_count=0
 mshrs=10
@@ -75,8 +74,7 @@ block_size=64
 compressed_bus=false
 compression_latency=0
 hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
 lifo=false
 max_miss_count=0
 mshrs=10
@@ -114,8 +112,7 @@ block_size=64
 compressed_bus=false
 compression_latency=0
 hash_delay=1
-hit_latency=1
-latency=1
+latency=10000
 lifo=false
 max_miss_count=0
 mshrs=10
@@ -147,6 +144,7 @@ mem_side=system.membus.port[1]
 
 [system.cpu.toL2Bus]
 type=Bus
+block_size=64
 bus_id=0
 clock=1000
 responder_set=false
@@ -171,6 +169,7 @@ uid=100
 
 [system.membus]
 type=Bus
+block_size=64
 bus_id=0
 clock=1000
 responder_set=false
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out
index 970fa6992..5d5cc71c1 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out
@@ -20,6 +20,7 @@ bus_id=0
 clock=1000
 width=64
 responder_set=false
+block_size=64
 
 [system.cpu.workload]
 type=LiveProcess
@@ -61,13 +62,14 @@ bus_id=0
 clock=1000
 width=64
 responder_set=false
+block_size=64
 
 [system.cpu.icache]
 type=BaseCache
 size=131072
 assoc=2
 block_size=64
-latency=1
+latency=1000
 mshrs=10
 tgts_per_mshr=5
 write_buffers=8
@@ -98,14 +100,13 @@ prefetch_policy=none
 prefetch_cache_check_push=true
 prefetch_use_cpu_id=true
 prefetch_data_accesses_only=false
-hit_latency=1
 
 [system.cpu.dcache]
 type=BaseCache
 size=262144
 assoc=2
 block_size=64
-latency=1
+latency=1000
 mshrs=10
 tgts_per_mshr=5
 write_buffers=8
@@ -136,14 +137,13 @@ prefetch_policy=none
 prefetch_cache_check_push=true
 prefetch_use_cpu_id=true
 prefetch_data_accesses_only=false
-hit_latency=1
 
 [system.cpu.l2cache]
 type=BaseCache
 size=2097152
 assoc=2
 block_size=64
-latency=1
+latency=10000
 mshrs=10
 tgts_per_mshr=5
 write_buffers=8
@@ -174,5 +174,4 @@ prefetch_policy=none
 prefetch_cache_check_push=true
 prefetch_use_cpu_id=true
 prefetch_data_accesses_only=false
-hit_latency=1
 
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
index 988dc8a7f..c95331047 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,41 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 462859                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 155288                       # Number of bytes of host memory used
-host_seconds                                  3715.16                       # Real time elapsed on the host
-host_tick_rate                              345995852                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 480485                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 155316                       # Number of bytes of host memory used
+host_seconds                                  3578.87                       # Real time elapsed on the host
+host_tick_rate                              745845171                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1719594534                       # Number of instructions simulated
-sim_seconds                                  1.285430                       # Number of seconds simulated
-sim_ticks                                1285429818500                       # Number of ticks simulated
+sim_seconds                                  2.669285                       # Number of seconds simulated
+sim_ticks                                2669284585000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          607807189                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency  3129.930590                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2129.930590                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 12893.226605                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11893.226605                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              594739458                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    40901091000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency   168485217000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.021500                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses             13067731                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  27833360000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 155417486000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.021500                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses        13067731                       # number of ReadReq MSHR misses
 system.cpu.dcache.SwapReq_accesses              15448                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency  3090.909091                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency  2090.909091                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency 13090.909091                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 12090.909091                       # average SwapReq mshr miss latency
 system.cpu.dcache.SwapReq_hits                  15437                       # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency          34000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency         144000                       # number of SwapReq miss cycles
 system.cpu.dcache.SwapReq_miss_rate          0.000712                       # miss rate for SwapReq accesses
 system.cpu.dcache.SwapReq_misses                   11                       # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency        23000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency       133000                       # number of SwapReq MSHR miss cycles
 system.cpu.dcache.SwapReq_mshr_miss_rate     0.000712                       # mshr miss rate for SwapReq accesses
 system.cpu.dcache.SwapReq_mshr_misses              11                       # number of SwapReq MSHR misses
 system.cpu.dcache.WriteReq_accesses         166970997                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency  2764.531806                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency  1764.531806                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 12404.292450                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11404.292450                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits             165264000                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    4719047500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   21174090000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.010223                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses             1706997                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   3012050500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency  19467093000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.010223                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses        1706997                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           774778186                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency  3087.714271                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  2087.714271                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 12836.737637                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 11836.737637                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits               760003458                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     45620138500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency    189659307000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.019070                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses              14774728                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  30845410500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 174884579000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.019070                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses         14774728                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses          774778186                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency  3087.714271                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  2087.714271                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 12836.737637                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 11836.737637                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits              760003458                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    45620138500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency   189659307000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.019070                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses             14774728                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  30845410500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 174884579000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.019070                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses        14774728                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements               14770643                       # number of replacements
 system.cpu.dcache.sampled_refs               14774739                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4094.607725                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4094.628585                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                760018895                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             1932183000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle             3913237000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                  4191356                       # number of writebacks
 system.cpu.icache.ReadReq_accesses         1719594535                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  3753.607103                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  2753.607103                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 13991.120977                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 12991.120977                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits             1719593634                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency        3382000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency       12606000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000001                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  901                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency      2481000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     11705000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000001                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             901                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses          1719594535                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  3753.607103                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  2753.607103                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 13991.120977                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 12991.120977                       # average overall mshr miss latency
 system.cpu.icache.demand_hits              1719593634                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency         3382000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency        12606000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000001                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   901                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency      2481000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     11705000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000001                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses              901                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses         1719594535                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  3753.607103                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  2753.607103                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 13991.120977                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 12991.120977                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits             1719593634                       # number of overall hits
-system.cpu.icache.overall_miss_latency        3382000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency       12606000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000001                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  901                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency      2481000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     11705000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000001                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses             901                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                     31                       # number of replacements
 system.cpu.icache.sampled_refs                    901                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                737.434314                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                737.715884                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1719593634                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.l2cache.ReadReq_accesses          14775639                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency  2607.028468                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1605.780536                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 12999.785859                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.785859                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits               8592784                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   16118879000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency   80375791000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.418449                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses             6182855                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   9928308213                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency  68010081000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.418449                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses        6182855                       # number of ReadReq MSHR misses
 system.cpu.l2cache.Writeback_accesses         4191356                       # number of Writeback accesses(hits+misses)
@@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses           14775639                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency  2607.028468                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency  1605.780536                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 12999.785859                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.785859                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                8592784                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    16118879000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency    80375791000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.418449                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses              6182855                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   9928308213                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  68010081000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_rate     0.418449                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses         6182855                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses          18966995                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency  2595.599252                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency  1605.780536                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 12942.794779                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.785859                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits              12756915                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   16118879000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency   80375791000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.327415                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses             6210080                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   9928308213                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  68010081000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_rate     0.325980                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses        6182855                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements               6150087                       # number of replacements
 system.cpu.l2cache.sampled_refs               6182855                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             26097.875810                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             26129.060966                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                12756915                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          390549075000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.warmup_cycle          806915893000                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                 1069081                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                     1285429818500                       # number of cpu cycles simulated
+system.cpu.numCycles                     2669284585000                       # number of cpu cycles simulated
 system.cpu.num_insts                       1719594534                       # Number of instructions executed
 system.cpu.num_refs                         774793634                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             632                       # Number of system calls
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
index d1c7d6062..272fc2ce1 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
@@ -25,9 +25,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 27 2007 14:35:32
-M5 started Fri Apr 27 15:24:20 2007
+M5 compiled May 15 2007 13:02:31
+M5 started Tue May 15 15:05:32 2007
 M5 executing on zizzer.eecs.umich.edu
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 1285429818500 because target called exit()
+Exiting @ tick 2669284585000 because target called exit()