diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:25 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:25 -0500 |
| commit | 1114be4b78c0855d96004b9f71c61d4b6a050d3a (patch) | |
| tree | eb1e2047d27bd31626530cae97cd9224e1dbbb11 /tests/long/10.mcf | |
| parent | 7dde557fdc51140988092962137e1006d1609bea (diff) | |
| download | gem5-1114be4b78c0855d96004b9f71c61d4b6a050d3a.tar.xz | |
O3: Update stats for memory order violation checking patch.
Diffstat (limited to 'tests/long/10.mcf')
| -rw-r--r-- | tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini | 4 | ||||
| -rwxr-xr-x | tests/long/10.mcf/ref/arm/linux/o3-timing/simout | 9 | ||||
| -rw-r--r-- | tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt | 756 | ||||
| -rw-r--r-- | tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini | 5 | ||||
| -rwxr-xr-x | tests/long/10.mcf/ref/x86/linux/o3-timing/simout | 11 | ||||
| -rw-r--r-- | tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt | 734 |
6 files changed, 760 insertions, 759 deletions
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini index a74b5cf43..4906aee98 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -496,9 +496,9 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout index 69008c385..800a14f70 100755 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 21:03:35 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Mar 18 2011 20:12:03 +M5 started Mar 18 2011 20:50:23 +M5 executing on zizzer command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +27,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 45750115000 because target called exit() +Exiting @ tick 44810819000 because target called exit() diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt index 012c275ff..59d8e7864 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 113142 # Simulator instruction rate (inst/s) -host_mem_usage 388016 # Number of bytes of host memory used -host_seconds 806.51 # Real time elapsed on the host -host_tick_rate 56726347 # Simulator tick rate (ticks/s) +host_inst_rate 152339 # Simulator instruction rate (inst/s) +host_mem_usage 354000 # Number of bytes of host memory used +host_seconds 598.99 # Real time elapsed on the host +host_tick_rate 74810841 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 91249480 # Number of instructions simulated -sim_seconds 0.045750 # Number of seconds simulated -sim_ticks 45750115000 # Number of ticks simulated +sim_insts 91249440 # Number of instructions simulated +sim_seconds 0.044811 # Number of seconds simulated +sim_ticks 44810819000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 25060777 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 26802034 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 13379 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1583014 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 23911601 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 29845348 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 62467 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 18706972 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 599512 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 24834182 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 26488589 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 13381 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1577083 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 23759439 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 29547808 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 61655 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 18706964 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 663516 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 85858585 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.062935 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.459577 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 84127548 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.084806 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.485867 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 40879742 47.61% 47.61% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 22675219 26.41% 74.02% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 9677073 11.27% 85.29% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 7600715 8.85% 94.15% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2662481 3.10% 97.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 219814 0.26% 97.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 922714 1.07% 98.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 621315 0.72% 99.30% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 599512 0.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 39814306 47.33% 47.33% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 21951452 26.09% 73.42% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 9558270 11.36% 84.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 7643193 9.09% 93.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2705607 3.22% 97.08% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 250022 0.30% 97.38% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 904462 1.08% 98.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 636720 0.76% 99.21% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 663516 0.79% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 85858585 # Number of insts commited each cycle -system.cpu.commit.COM:count 91262089 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 84127548 # Number of insts commited each cycle +system.cpu.commit.COM:count 91262049 # Number of instructions committed system.cpu.commit.COM:fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 56148 # Number of function calls committed. -system.cpu.commit.COM:int_insts 72532978 # Number of committed integer instructions. -system.cpu.commit.COM:loads 22575791 # Number of loads committed +system.cpu.commit.COM:int_insts 72532946 # Number of committed integer instructions. +system.cpu.commit.COM:loads 22575783 # Number of loads committed system.cpu.commit.COM:membars 3888 # Number of memory barriers committed -system.cpu.commit.COM:refs 27322459 # Number of memory references committed +system.cpu.commit.COM:refs 27322443 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1602069 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 91262089 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 554321 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 39090054 # The number of squashed insts skipped by commit -system.cpu.committedInsts 91249480 # Number of Instructions Simulated -system.cpu.committedInsts_total 91249480 # Number of Instructions Simulated -system.cpu.cpi 1.002748 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.002748 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 6707 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 17642.857143 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 6700 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 123500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.001044 # miss rate for LoadLockedReq accesses +system.cpu.commit.branchMispredicts 1596327 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 91262049 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 554313 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 37919647 # The number of squashed insts skipped by commit +system.cpu.committedInsts 91249440 # Number of Instructions Simulated +system.cpu.committedInsts_total 91249440 # Number of Instructions Simulated +system.cpu.cpi 0.982161 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.982161 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 6690 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 17714.285714 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_hits 6683 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 124000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.001046 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 24501880 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5328.400499 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2255.904510 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23546851 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5088777000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.038978 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 955029 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 51059 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2039270000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.036894 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 903970 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 5711 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 5711 # number of StoreCondReq hits +system.cpu.dcache.ReadReq_accesses 24486290 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5359.849313 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2292.924521 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23465767 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5469849500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.041677 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1020523 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 105108 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2098977500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.037385 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 915415 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 5703 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 5703 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 24088.951664 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 22495.719344 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 4561444 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4180324405 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.036650 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 173537 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 127274 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1040719464 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009770 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 46263 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2889.691936 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 26966.662287 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 29146.815533 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 4581638 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4135148895 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.032385 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 153343 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 118616 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1012181463 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.007334 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 34727 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2888.268241 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 29.593485 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 7453 # number of cycles access was blocked +system.cpu.dcache.avg_refs 29.532208 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 7497 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 21536874 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 21653347 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29236861 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 8213.167334 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3241.299201 # average overall mshr miss latency -system.cpu.dcache.demand_hits 28108295 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 9269101405 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.038601 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1128566 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 178333 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3079989464 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.032501 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 950233 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 29221271 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 8182.363570 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3274.414733 # average overall mshr miss latency +system.cpu.dcache.demand_hits 28047405 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 9604998395 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.040172 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1173866 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 223724 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3111158963 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.032515 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 950142 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.852939 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 3493.638101 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 29236861 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 8213.167334 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3241.299201 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.852969 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 3493.759701 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 29221271 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 8182.363570 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3274.414733 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 28108295 # number of overall hits -system.cpu.dcache.overall_miss_latency 9269101405 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.038601 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1128566 # number of overall misses -system.cpu.dcache.overall_mshr_hits 178333 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3079989464 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.032501 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 950233 # number of overall MSHR misses +system.cpu.dcache.overall_hits 28047405 # number of overall hits +system.cpu.dcache.overall_miss_latency 9604998395 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.040172 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1173866 # number of overall misses +system.cpu.dcache.overall_mshr_hits 223724 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3111158963 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.032515 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 950142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 946137 # number of replacements -system.cpu.dcache.sampled_refs 950233 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 946046 # number of replacements +system.cpu.dcache.sampled_refs 950142 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3493.638101 # Cycle average of tags in use -system.cpu.dcache.total_refs 28120706 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 19296981000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 943150 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 18515611 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 9136 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4758893 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 141080898 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 33469255 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 33017602 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 5612232 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 30592 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 856116 # Number of cycles decode is unblocking +system.cpu.dcache.tagsinuse 3493.759701 # Cycle average of tags in use +system.cpu.dcache.total_refs 28059791 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 18895308000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 943121 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 17616091 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 8947 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4756283 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 139877523 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 32952944 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 32754638 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 5463778 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 29965 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 803874 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,81 +158,81 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 29845348 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 15520576 # Number of cache lines fetched -system.cpu.fetch.Cycles 34753915 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 276813 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 143294690 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 20423 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 1615761 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.326178 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 15520576 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 25123244 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.566058 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 91470816 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.578120 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.573721 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 29547808 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 15301199 # Number of cache lines fetched +system.cpu.fetch.Cycles 34415849 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 249988 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 142060699 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 19814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1615180 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.329695 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 15301199 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 24895837 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.585116 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 89591325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.597262 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.585030 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 56780865 62.08% 62.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6426529 7.03% 69.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6459161 7.06% 76.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4449430 4.86% 81.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3594685 3.93% 84.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1897731 2.07% 87.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1934782 2.12% 89.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3238407 3.54% 92.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6689226 7.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 55239268 61.66% 61.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6349932 7.09% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6414208 7.16% 75.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4426055 4.94% 80.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3460419 3.86% 84.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1907279 2.13% 86.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1921135 2.14% 88.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3244772 3.62% 92.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6628257 7.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 91470816 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 87 # number of floating regfile reads -system.cpu.fp_regfile_writes 78 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 15520576 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35610.047847 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34405.604720 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 15519740 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 29770000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000054 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 836 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 158 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 23327000 # number of ReadReq MSHR miss cycles +system.cpu.fetch.rateDist::total 89591325 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 83 # number of floating regfile reads +system.cpu.fp_regfile_writes 76 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 15301199 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35691.320293 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34369.469027 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 15300381 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 29195500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000053 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 818 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 140 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 23302500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000044 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 678 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 22890.471976 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 22566.933628 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 15520576 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35610.047847 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34405.604720 # average overall mshr miss latency -system.cpu.icache.demand_hits 15519740 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 29770000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000054 # miss rate for demand accesses -system.cpu.icache.demand_misses 836 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 158 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 23327000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_accesses 15301199 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35691.320293 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34369.469027 # average overall mshr miss latency +system.cpu.icache.demand_hits 15300381 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 29195500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000053 # miss rate for demand accesses +system.cpu.icache.demand_misses 818 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 140 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 23302500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000044 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 678 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.276985 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 567.265894 # Average occupied blocks per context -system.cpu.icache.overall_accesses 15520576 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35610.047847 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34405.604720 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.276968 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 567.230284 # Average occupied blocks per context +system.cpu.icache.overall_accesses 15301199 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35691.320293 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34369.469027 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 15519740 # number of overall hits -system.cpu.icache.overall_miss_latency 29770000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000054 # miss rate for overall accesses -system.cpu.icache.overall_misses 836 # number of overall misses -system.cpu.icache.overall_mshr_hits 158 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 23327000 # number of overall MSHR miss cycles +system.cpu.icache.overall_hits 15300381 # number of overall hits +system.cpu.icache.overall_miss_latency 29195500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000053 # miss rate for overall accesses +system.cpu.icache.overall_misses 818 # number of overall misses +system.cpu.icache.overall_mshr_hits 140 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 23302500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000044 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 678 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -240,161 +240,161 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 2 # number of replacements system.cpu.icache.sampled_refs 678 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 567.265894 # Cycle average of tags in use -system.cpu.icache.total_refs 15519740 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 567.230284 # Cycle average of tags in use +system.cpu.icache.total_refs 15300381 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 29415 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 20970115 # Number of branches executed -system.cpu.iew.EXEC:nop 54598 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.133641 # Inst execution rate -system.cpu.iew.EXEC:refs 30199659 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 5140774 # Number of stores executed +system.cpu.idleCycles 30314 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 20925598 # Number of branches executed +system.cpu.iew.EXEC:nop 54439 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.157971 # Inst execution rate +system.cpu.iew.EXEC:refs 30252486 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 5191190 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 127211016 # num instructions consuming a value -system.cpu.iew.WB:count 102056385 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.487951 # average fanout of values written-back +system.cpu.iew.WB:consumers 127253538 # num instructions consuming a value +system.cpu.iew.WB:count 102147077 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.488789 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 62072763 # num instructions producing a value -system.cpu.iew.WB:rate 1.115368 # insts written-back per cycle -system.cpu.iew.WB:sent 102572716 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1825852 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 421320 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 32016564 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 690308 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 299404 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 6585994 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 130352707 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 25058885 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2046100 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 103728443 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 170905 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 62200099 # num instructions producing a value +system.cpu.iew.WB:rate 1.139759 # insts written-back per cycle +system.cpu.iew.WB:sent 102625765 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 1807591 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 317265 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 31522248 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 688638 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 326826 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 6607421 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 129183212 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 25061296 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2026821 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 103779294 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 171143 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1567 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 5612232 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 206705 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 178 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 5463778 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 193382 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 21484 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 353411 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 19757 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 21870 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 400446 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 24865 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 3168 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 14115 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 9440772 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1839326 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 3168 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 298332 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1527520 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 259522598 # number of integer regfile reads -system.cpu.int_regfile_writes 80481877 # number of integer regfile writes -system.cpu.ipc 0.997260 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.997260 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.squashedLoads 8946464 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1860761 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 14115 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 301414 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1506177 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 259793995 # number of integer regfile reads +system.cpu.int_regfile_writes 80578248 # number of integer regfile writes +system.cpu.ipc 1.018163 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.018163 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 74292294 70.24% 70.24% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 10639 0.01% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 1 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 21 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 38 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 4 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 70.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 26262906 24.83% 95.08% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 5208640 4.92% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 74302206 70.22% 70.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 10686 0.01% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 1 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 21 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 70.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 37 0.00% 70.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 70.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 4 0.00% 70.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 70.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 26235832 24.80% 95.03% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 5257328 4.97% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 105774543 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 160185 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.001514 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 105806115 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 187983 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.001777 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 52262 32.63% 32.63% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 27 0.02% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 32.64% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 62957 39.30% 71.95% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 44939 28.05% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 52416 27.88% 27.88% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 27 0.01% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 27.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 77701 41.33% 69.23% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 57839 30.77% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 91470816 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.156375 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.444584 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 89591325 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.180986 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.458768 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 39774696 43.48% 43.48% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 24298391 26.56% 70.05% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 14242553 15.57% 85.62% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 6365982 6.96% 92.58% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 2257550 2.47% 95.05% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2688100 2.94% 97.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1607594 1.76% 99.74% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 110764 0.12% 99.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 125186 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 38472986 42.94% 42.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 23460608 26.19% 69.13% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 14306679 15.97% 85.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 6444522 7.19% 92.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 2370548 2.65% 94.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 2667663 2.98% 97.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 1626344 1.82% 99.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 115788 0.13% 99.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 126187 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 91470816 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.156003 # Inst issue rate -system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 190 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 87 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 166 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 105934631 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 303205662 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 102056298 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 169015166 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 129602907 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 105774543 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 695202 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 38714982 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 25765 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 140881 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 72800988 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 89591325 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.180587 # Inst issue rate +system.cpu.iq.fp_alu_accesses 94 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 184 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 84 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 160 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 105994004 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 301419127 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 102146993 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 166681021 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 128435251 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 105806115 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 693522 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 37544982 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 27773 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 139209 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 69554944 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -416,107 +416,107 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 46263 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34215.214251 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31037.691726 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 31724 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 497455000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.314268 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_accesses 34763 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34229.176697 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31038.826604 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 20224 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 497658000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.418232 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 14539 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 451257000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.314268 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 451273500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.418232 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 14539 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 904648 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34281.219272 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31102.589641 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 903631 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 34864000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.001124 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1017 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 13 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 31227000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001110 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_accesses 916057 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34296.259843 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31108.565737 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 915041 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 34845000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.001109 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1016 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 31233000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001096 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 1004 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 943150 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 943150 # number of Writeback hits +system.cpu.l2cache.Writeback_accesses 943121 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 943121 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 102.932573 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 104.841512 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 950911 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34219.529442 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31041.883806 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 935355 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 532319000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.016359 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 15556 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 482484000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.016345 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_accesses 950820 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34233.558341 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31043.331403 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 935265 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 532503000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.016360 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 15555 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 482506500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.016347 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 15543 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.012326 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.249116 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 403.905799 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 8163.029985 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 950911 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34219.529442 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31041.883806 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.012390 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.250098 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 405.999438 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 8195.227045 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 950820 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34233.558341 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31043.331403 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 935355 # number of overall hits -system.cpu.l2cache.overall_miss_latency 532319000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.016359 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 15556 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 13 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 482484000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.016345 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_hits 935265 # number of overall hits +system.cpu.l2cache.overall_miss_latency 532503000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.016360 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 15555 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 12 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 482506500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.016347 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 15543 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 704 # number of replacements +system.cpu.l2cache.replacements 702 # number of replacements system.cpu.l2cache.sampled_refs 15528 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8566.935784 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1598337 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 8601.226483 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1627979 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 32 # number of writebacks -system.cpu.memDep0.conflictingLoads 1440720 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1005315 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 32016564 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6585994 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 198555291 # number of misc regfile reads +system.cpu.memDep0.conflictingLoads 745583 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 374535 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 31522248 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6607421 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 197265421 # number of misc regfile reads system.cpu.misc_regfile_writes 1603310 # number of misc regfile writes -system.cpu.numCycles 91500231 # number of cpu cycles simulated +system.cpu.numCycles 89621639 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 3003526 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 72121263 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2932731 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 36158864 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2288265 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:BlockCycles 2572422 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 72121223 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 2896922 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 35550108 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1943384 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 58 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 352780022 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 136654080 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 107391797 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 31135789 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 5612232 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 6274602 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 35270531 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 655 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 352779367 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 9285803 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 702152 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 13506306 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 702838 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 215605482 # The number of ROB reads -system.cpu.rob.rob_writes 266316908 # The number of ROB writes -system.cpu.timesIdled 1399 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:RenameLookups 350234554 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 135614727 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 106518917 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 30912538 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 5463778 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5897124 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 34397691 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 648 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 350233906 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 9195355 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 700993 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 13077041 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 701919 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 212639994 # The number of ROB reads +system.cpu.rob.rob_writes 263827329 # The number of ROB writes +system.cpu.timesIdled 1459 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 442 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini index 31cbafe2a..1f2e75864 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -115,6 +115,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -413,6 +414,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -448,6 +450,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 @@ -488,7 +491,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing +cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout index 41587c0af..2b45d7376 100755 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 12 2011 02:22:23 -M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch -M5 started Feb 12 2011 02:22:27 -M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing +M5 compiled Mar 18 2011 20:12:06 +M5 started Mar 18 2011 20:12:16 +M5 executing on zizzer +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +27,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 98622214000 because target called exit() +Exiting @ tick 81396224000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt index 33b45551d..2d839c8d9 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 133029 # Simulator instruction rate (inst/s) -host_mem_usage 371192 # Number of bytes of host memory used -host_seconds 2091.22 # Real time elapsed on the host -host_tick_rate 47160241 # Simulator tick rate (ticks/s) +host_inst_rate 173311 # Simulator instruction rate (inst/s) +host_mem_usage 350460 # Number of bytes of host memory used +host_seconds 1605.16 # Real time elapsed on the host +host_tick_rate 50708988 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192519 # Number of instructions simulated -sim_seconds 0.098622 # Number of seconds simulated -sim_ticks 98622214000 # Number of ticks simulated +sim_seconds 0.081396 # Number of seconds simulated +sim_ticks 81396224000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 44152407 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 44769192 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 38238795 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 38788801 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 3292099 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 50608102 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 50608102 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 2465320 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 43504790 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 43504790 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 29309710 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 11603540 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 13548841 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 176948364 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.572168 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.280995 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 149131695 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.865415 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.481905 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 83964580 47.45% 47.45% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 36146762 20.43% 67.88% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 16087394 9.09% 76.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 14069173 7.95% 84.92% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 7224288 4.08% 89.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 2649535 1.50% 90.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 3731341 2.11% 92.61% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 1471751 0.83% 93.44% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 11603540 6.56% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 63516016 42.59% 42.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 27005826 18.11% 60.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 19486009 13.07% 73.77% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 13132636 8.81% 82.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 4245933 2.85% 85.42% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 3434891 2.30% 87.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 3062949 2.05% 89.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 1698594 1.14% 90.91% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 13548841 9.09% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 176948364 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 149131695 # Number of insts commited each cycle system.cpu.commit.COM:count 278192519 # Number of instructions committed system.cpu.commit.COM:fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,344 +44,344 @@ system.cpu.commit.COM:loads 90779388 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 122219139 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 3292117 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 2465329 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 130955012 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 88842299 # The number of squashed insts skipped by commit system.cpu.committedInsts 278192519 # Number of Instructions Simulated system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated -system.cpu.cpi 0.709021 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.709021 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 69458873 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 6142.707591 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3039.983703 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 67343989 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12991114000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.030448 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 2114884 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 142693 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 5995428500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.028394 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1972191 # number of ReadReq MSHR misses +system.cpu.cpi 0.585179 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.585179 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 63345837 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 6389.837562 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2805.424936 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 61126773 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 14179458500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.035031 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 2219064 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 247059 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 5532312000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.031131 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1972005 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 17842.235128 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17696.947420 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 31210017 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4098968045 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.007307 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 229734 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 123609 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1878088545 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003376 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 106125 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3358.823529 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 17790.751735 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17644.271587 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 31202641 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4218365144 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.007542 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 237110 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 131111 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1870275144 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003371 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 105999 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3445.783133 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 47.420176 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 85 # number of cycles access was blocked +system.cpu.dcache.avg_refs 44.431869 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 83 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 285500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 286000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 100898624 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7289.068857 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3788.411890 # average overall mshr miss latency -system.cpu.dcache.demand_hits 98554006 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 17090082045 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.023237 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2344618 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 266302 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 7873517045 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.020598 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2078316 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 94785588 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 7490.439865 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3562.354617 # average overall mshr miss latency +system.cpu.dcache.demand_hits 92329414 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 18397823644 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.025913 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2456174 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 378170 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 7402587144 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.021923 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2078004 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.994974 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4075.414607 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 100898624 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7289.068857 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3788.411890 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.994940 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4075.274681 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 94785588 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 7490.439865 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3562.354617 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 98554006 # number of overall hits -system.cpu.dcache.overall_miss_latency 17090082045 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.023237 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2344618 # number of overall misses -system.cpu.dcache.overall_mshr_hits 266302 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 7873517045 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.020598 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2078316 # number of overall MSHR misses +system.cpu.dcache.overall_hits 92329414 # number of overall hits +system.cpu.dcache.overall_miss_latency 18397823644 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.025913 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2456174 # number of overall misses +system.cpu.dcache.overall_mshr_hits 378170 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 7402587144 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.021923 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2078004 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2074218 # number of replacements -system.cpu.dcache.sampled_refs 2078314 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2073904 # number of replacements +system.cpu.dcache.sampled_refs 2078000 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4075.414607 # Cycle average of tags in use -system.cpu.dcache.total_refs 98554015 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40655663000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 1442059 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 21837286 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 443283148 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 77587406 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 75762450 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 19022168 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 1761222 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 50608102 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 34652495 # Number of cache lines fetched -system.cpu.fetch.Cycles 82344495 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 326035 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 259681215 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 35 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 3883025 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.256576 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 34652495 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 44152407 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.316545 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 195970532 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.323843 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.188074 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4075.274681 # Cycle average of tags in use +system.cpu.dcache.total_refs 92329423 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 30396735000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 1448011 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 13645155 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 390459172 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 68124952 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 66154578 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 12492114 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 1207010 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 43504790 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 30855910 # Number of cache lines fetched +system.cpu.fetch.Cycles 71218247 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 310077 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 225429246 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 21 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 2638813 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.267241 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 30855910 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 38238795 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.384765 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 161623809 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.462324 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.240695 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 116145210 59.27% 59.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6750085 3.44% 62.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3016102 1.54% 64.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 8362073 4.27% 68.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7646936 3.90% 72.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6348764 3.24% 75.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 9080088 4.63% 80.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8246058 4.21% 84.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 30375216 15.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 92912734 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4821587 2.98% 60.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3003433 1.86% 62.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6267047 3.88% 66.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7344013 4.54% 70.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5575474 3.45% 74.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 8028911 4.97% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 6451248 3.99% 83.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 27219362 16.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 195970532 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 161623809 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 75 # number of floating regfile reads system.cpu.fp_regfile_writes 41 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 34652495 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35675.242356 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35201.684836 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 34651154 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 47840500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1341 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 332 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 35518500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000029 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1009 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 30855910 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36182.458888 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35209.772952 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 30854633 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 46205000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000041 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1277 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 264 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 35667500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000033 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 1013 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 34376.144841 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 30488.767787 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 34652495 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35675.242356 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35201.684836 # average overall mshr miss latency -system.cpu.icache.demand_hits 34651154 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 47840500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000039 # miss rate for demand accesses -system.cpu.icache.demand_misses 1341 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 35518500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000029 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1009 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 30855910 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36182.458888 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35209.772952 # average overall mshr miss latency +system.cpu.icache.demand_hits 30854633 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 46205000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000041 # miss rate for demand accesses +system.cpu.icache.demand_misses 1277 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 264 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 35667500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000033 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 1013 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.392466 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 803.770978 # Average occupied blocks per context -system.cpu.icache.overall_accesses 34652495 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35675.242356 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35201.684836 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.396500 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 812.031019 # Average occupied blocks per context +system.cpu.icache.overall_accesses 30855910 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36182.458888 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35209.772952 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 34651154 # number of overall hits -system.cpu.icache.overall_miss_latency 47840500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000039 # miss rate for overall accesses -system.cpu.icache.overall_misses 1341 # number of overall misses -system.cpu.icache.overall_mshr_hits 332 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 35518500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1009 # number of overall MSHR misses +system.cpu.icache.overall_hits 30854633 # number of overall hits +system.cpu.icache.overall_miss_latency 46205000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000041 # miss rate for overall accesses +system.cpu.icache.overall_misses 1277 # number of overall misses +system.cpu.icache.overall_mshr_hits 264 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 35667500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000033 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 1013 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 60 # number of replacements -system.cpu.icache.sampled_refs 1008 # Sample count of references to valid blocks. +system.cpu.icache.replacements 63 # number of replacements +system.cpu.icache.sampled_refs 1012 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 803.770978 # Cycle average of tags in use -system.cpu.icache.total_refs 34651154 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 812.031019 # Cycle average of tags in use +system.cpu.icache.total_refs 30854633 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1273897 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 33755681 # Number of branches executed +system.cpu.idleCycles 1168640 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 32808514 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.719732 # Inst execution rate -system.cpu.iew.EXEC:refs 143271490 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 33964004 # Number of stores executed +system.cpu.iew.EXEC:rate 2.009454 # Inst execution rate +system.cpu.iew.EXEC:refs 141715314 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 34352421 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 356152066 # num instructions consuming a value -system.cpu.iew.WB:count 334303723 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.713943 # average fanout of values written-back +system.cpu.iew.WB:consumers 330470543 # num instructions consuming a value +system.cpu.iew.WB:count 324204287 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.735351 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 254272214 # num instructions producing a value -system.cpu.iew.WB:rate 1.694870 # insts written-back per cycle -system.cpu.iew.WB:sent 336664522 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 3987132 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 754395 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 138835558 # Number of dispatched load instructions +system.cpu.iew.WB:producers 243011799 # num instructions producing a value +system.cpu.iew.WB:rate 1.991519 # insts written-back per cycle +system.cpu.iew.WB:sent 325408414 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2866285 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 739357 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 121527888 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 663120 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 42750154 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 409142439 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 109307486 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6572046 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 339207523 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2275 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 440749 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 39643183 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 367028456 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 107362893 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4685170 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 327123971 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 4283 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 78833 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 19022168 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 104797 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 66782 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 12492114 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 101572 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 14565 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 39666706 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 30063 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 14164 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 43812375 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 37185 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 1469253 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 2742 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 48056170 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 11310403 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 1469253 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 865481 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 3121651 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 577634708 # number of integer regfile reads -system.cpu.int_regfile_writes 302216415 # number of integer regfile writes -system.cpu.ipc 1.410395 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.410395 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16702 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 200471700 57.98% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 15 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 57.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 110857049 32.06% 90.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 34434103 9.96% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 237293 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 3275 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 30748500 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 8203432 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 237293 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 582972 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2283313 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 572686347 # number of integer regfile reads +system.cpu.int_regfile_writes 291536884 # number of integer regfile writes +system.cpu.ipc 1.708879 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.708879 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16703 0.01% 0.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 188329198 56.76% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 16 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 108641887 32.74% 89.51% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 34821337 10.49% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 345779569 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 4109732 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011885 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 331809141 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 1744992 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.005259 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 26819 0.65% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 3817756 92.90% 93.55% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 265157 6.45% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 20475 1.17% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 1576903 90.37% 91.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 147614 8.46% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 195970532 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.764447 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.745109 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 161623809 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 2.052972 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.792191 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 63955785 32.64% 32.64% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 38956843 19.88% 52.51% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 30997952 15.82% 68.33% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 27554899 14.06% 82.39% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 19728653 10.07% 92.46% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 8783605 4.48% 96.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 3191043 1.63% 98.57% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 2230786 1.14% 99.71% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 570966 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 44438080 27.49% 27.49% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 26560474 16.43% 43.93% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 27560184 17.05% 60.98% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 26726118 16.54% 77.52% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 19530475 12.08% 89.60% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 11104171 6.87% 96.47% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 3863575 2.39% 98.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 1600116 0.99% 99.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 240616 0.15% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 195970532 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.753051 # Inst issue rate -system.cpu.iq.fp_alu_accesses 110 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 224 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 83 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 263 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 349872489 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 891669703 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 334303640 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 540919004 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 409141974 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 345779569 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 161623809 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 2.038234 # Inst issue rate +system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 208 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 80 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 238 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 333537329 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 827162429 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 324204207 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 455842500 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 367027991 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 331809141 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 465 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 130872312 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 30525 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 88592670 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 175554 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 221868127 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 106126 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34139.167845 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31050.412541 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 63706 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 1448183500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.399714 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 42420 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1317158500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.399714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 42420 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1973197 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34279.521718 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31013.978995 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1938824 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1178290000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.017420 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 34373 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1066043500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017420 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 34373 # number of ReadReq MSHR misses +system.cpu.iq.iqSquashedOperandsExamined 124945161 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 106011 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34192.017786 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31115.893095 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 63955 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 1437979500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.396714 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 42056 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1308610000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.396714 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 42056 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1973004 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34215.506485 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31023.372893 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1938541 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1179169000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.017467 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 34463 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1069158500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017467 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 34463 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses @@ -389,85 +389,85 @@ system.cpu.l2cache.UpgradeReq_misses 1 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 1442058 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 1442058 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2176.470588 # average number of cycles each access was blocked +system.cpu.l2cache.Writeback_accesses 1448011 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1448011 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 42.835533 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 17 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 43.067418 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 37000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 35000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2079323 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34201.991067 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31034.104671 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2002530 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2626473500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.036932 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 76793 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 2079015 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34202.596741 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31074.223395 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2002496 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 2617148500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.036805 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 76519 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2383202000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.036932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 76793 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2377768500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.036805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 76519 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.185144 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.337522 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 6066.784489 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 11059.931141 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 2079323 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34201.991067 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31034.104671 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.196368 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.354446 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 6434.571377 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 11614.477696 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 2079015 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34202.596741 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31074.223395 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2002530 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2626473500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.036932 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 76793 # number of overall misses +system.cpu.l2cache.overall_hits 2002496 # number of overall hits +system.cpu.l2cache.overall_miss_latency 2617148500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.036805 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 76519 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2383202000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.036932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 76793 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2377768500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.036805 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 76519 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 49342 # number of replacements -system.cpu.l2cache.sampled_refs 77347 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 49066 # number of replacements +system.cpu.l2cache.sampled_refs 77071 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17126.715630 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3313200 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18049.049074 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3319249 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 29450 # number of writebacks -system.cpu.memDep0.conflictingLoads 87882428 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 16100005 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 138835558 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42750154 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 218323859 # number of misc regfile reads -system.cpu.numCycles 197244429 # number of cpu cycles simulated +system.cpu.l2cache.writebacks 29185 # number of writebacks +system.cpu.memDep0.conflictingLoads 49162785 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10611644 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 121527888 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 39643183 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 211169577 # number of misc regfile reads +system.cpu.numCycles 162792449 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 6557218 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 3023364 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 248344192 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 228138 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 83203716 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 14824029 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 13 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 1059543178 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 431467970 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 388798641 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 71280917 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 19022168 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 15900092 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 140454449 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 574 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 1059542604 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 6421 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 469 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 38067869 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 463 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 574492355 # The number of ROB reads -system.cpu.rob.rob_writes 837321831 # The number of ROB writes -system.cpu.timesIdled 40675 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 130274 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 72054036 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 9710787 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 941229334 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 383108308 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 343773743 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 63044913 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 12492114 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 11002939 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 95429551 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 586 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 941228748 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 6443 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 468 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 25868384 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 462 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 502617672 # The number of ROB reads +system.cpu.rob.rob_writes 746575877 # The number of ROB writes +system.cpu.timesIdled 40062 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- |