X86: Add x86 reference output for the timing CPU.

5 files changed, 1462 insertions, 0 deletions

diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
new file mode 100644
index 000000000..106b52826
--- /dev/null
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -0,0 +1,193 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+clock=500
+cpu_id=0
+defer_registration=false
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+cpu_side_filter_ranges=
+hash_delay=1
+latency=1000
+max_miss_count=0
+mem_side_filter_ranges=
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=X86DTB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+cpu_side_filter_ranges=
+hash_delay=1
+latency=1000
+max_miss_count=0
+mem_side_filter_ranges=
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=X86ITB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+cpu_side_filter_ranges=
+hash_delay=1
+latency=10000
+max_miss_count=0
+mem_side_filter_ranges=
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt
new file mode 100644
index 000000000..21761f34b
--- /dev/null
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt
@@ -0,0 +1,234 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate                                1094085                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 336424                       # Number of bytes of host memory used
+host_seconds                                   246.51                       # Real time elapsed on the host
+host_tick_rate                             2009645019                       # Simulator tick rate (ticks/s)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                   269697303                       # Number of instructions simulated
+sim_seconds                                  0.495388                       # Number of seconds simulated
+sim_ticks                                495387670000                       # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses           90779443                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 15899.099984                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12899.099984                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits               88829255                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    31006234000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.021483                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses              1950188                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  25155670000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.021483                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses         1950188                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses          31439750                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 55999.899641                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.899641                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              31210573                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   12833889000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.007289                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              229177                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency  12146358000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.007289                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         229177                       # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                  58.501856                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.demand_accesses           122219193                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 20116.007644                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 17116.007644                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               120039828                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     43840123000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.017832                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               2179365                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency  37302028000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.017832                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          2179365                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses          122219193                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 20116.007644                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 17116.007644                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits              120039828                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    43840123000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.017832                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              2179365                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency  37302028000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.017832                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         2179365                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements                2049944                       # number of replacements
+system.cpu.dcache.sampled_refs                2054040                       # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse               4078.630642                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                120165153                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle           165919745000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   229129                       # number of writebacks
+system.cpu.icache.ReadReq_accesses          331463335                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits              331462528                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency       45192000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.000002                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                  807                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency     42771000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000002                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses             807                       # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.icache.avg_refs               410734.235440                       # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.demand_accesses           331463335                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
+system.cpu.icache.demand_hits               331462528                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency        45192000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.000002                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                   807                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency     42771000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.000002                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses              807                       # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses          331463335                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits              331462528                       # number of overall hits
+system.cpu.icache.overall_miss_latency       45192000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.000002                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                  807                       # number of overall misses
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency     42771000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.000002                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses             807                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements                     24                       # number of replacements
+system.cpu.icache.sampled_refs                    807                       # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse                666.116249                       # Cycle average of tags in use
+system.cpu.icache.total_refs                331462528                       # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.l2cache.ReadExReq_accesses          103852                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency   5400304000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses            103852                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   4154080000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses       103852                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses           1950995                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits               1862007                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    4627376000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.045612                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               88988                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   3559520000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.045612                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          88988                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses         125325                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51990.456812                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency   6515704000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses           125325                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency   5013000000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses       125325                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          229129                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              229129                       # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs                 13.678221                       # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.demand_accesses            2054847                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                1862007                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency    10027680000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.093846                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses               192840                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency   7713600000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.093846                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses          192840                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses           2054847                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits               1862007                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency   10027680000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.093846                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses              192840                       # number of overall misses
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency   7713600000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.093846                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses         192840                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements                108885                       # number of replacements
+system.cpu.l2cache.sampled_refs                132827                       # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse             18052.553825                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1816837                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                   70892                       # number of writebacks
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.numCycles                        990775340                       # number of cpu cycles simulated
+system.cpu.num_insts                        269697303                       # Number of instructions executed
+system.cpu.num_refs                         124054655                       # Number of memory references
+system.cpu.workload.PROG:num_syscalls             444                       # Number of system calls
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out b/tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out
new file mode 100644
index 000000000..095132477
--- /dev/null
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out
@@ -0,0 +1,999 @@
+()
+500
+()
+499
+()
+498
+()
+496
+()
+495
+()
+494
+()
+493
+()
+492
+()
+491
+()
+490
+()
+489
+()
+488
+()
+487
+()
+486
+()
+484
+()
+482
+()
+481
+()
+480
+()
+479
+()
+478
+()
+477
+()
+476
+()
+475
+()
+474
+()
+473
+()
+472
+()
+471
+()
+469
+()
+468
+()
+467
+()
+466
+()
+465
+()
+464
+()
+463
+()
+462
+()
+461
+()
+460
+()
+459
+()
+458
+()
+457
+()
+455
+()
+454
+()
+452
+()
+451
+()
+450
+()
+449
+()
+448
+()
+446
+()
+445
+()
+444
+()
+443
+()
+442
+()
+440
+()
+439
+()
+438
+()
+436
+()
+435
+()
+433
+()
+432
+()
+431
+()
+428
+()
+427
+()
+425
+()
+424
+()
+423
+()
+420
+()
+419
+()
+416
+()
+414
+()
+413
+()
+412
+()
+407
+()
+406
+()
+405
+()
+404
+()
+403
+()
+402
+()
+401
+()
+400
+()
+399
+()
+398
+()
+396
+()
+395
+()
+393
+()
+392
+()
+390
+()
+389
+()
+388
+()
+387
+()
+386
+()
+385
+()
+384
+()
+383
+()
+382
+()
+381
+()
+380
+()
+379
+()
+377
+()
+375
+()
+374
+()
+373
+()
+372
+()
+371
+()
+370
+()
+369
+()
+368
+()
+366
+()
+365
+()
+364
+()
+362
+()
+361
+()
+360
+()
+359
+()
+358
+()
+357
+()
+356
+()
+355
+()
+354
+()
+352
+()
+350
+()
+347
+()
+344
+()
+342
+()
+341
+()
+340
+()
+339
+()
+338
+()
+332
+()
+325
+()
+320
+***
+345
+()
+319
+***
+497
+()
+318
+***
+349
+()
+317
+***
+408
+()
+316
+***
+324
+()
+315
+***
+328
+()
+314
+***
+335
+()
+313
+***
+378
+()
+312
+***
+426
+()
+311
+***
+411
+()
+304
+***
+343
+()
+303
+***
+417
+()
+302
+***
+485
+()
+301
+***
+363
+()
+300
+***
+376
+()
+299
+***
+333
+()
+292
+***
+337
+()
+291
+***
+409
+()
+290
+***
+421
+()
+289
+***
+437
+()
+288
+***
+430
+()
+287
+***
+348
+()
+286
+***
+326
+()
+284
+()
+282
+***
+308
+()
+279
+***
+297
+***
+305
+()
+278
+()
+277
+***
+307
+()
+276
+***
+296
+()
+273
+()
+271
+()
+265
+()
+246
+***
+267
+()
+245
+***
+280
+()
+244
+***
+391
+()
+243
+***
+330
+()
+242
+***
+456
+()
+241
+***
+346
+()
+240
+***
+483
+()
+239
+***
+260
+()
+238
+***
+261
+()
+237
+***
+262
+***
+294
+()
+236
+***
+253
+()
+229
+***
+397
+()
+228
+***
+298
+()
+227
+***
+415
+()
+226
+***
+264
+()
+224
+***
+232
+()
+222
+***
+233
+()
+217
+***
+250
+()
+211
+***
+331
+()
+210
+***
+394
+()
+209
+***
+410
+()
+208
+***
+321
+()
+207
+***
+327
+()
+206
+***
+309
+()
+199
+***
+259
+()
+198
+***
+219
+()
+197
+***
+220
+()
+195
+***
+429
+()
+194
+***
+470
+()
+193
+***
+274
+()
+191
+***
+203
+()
+190
+***
+263
+()
+189
+215
+***
+230
+()
+188
+***
+266
+***
+295
+()
+182
+***
+329
+()
+181
+***
+351
+()
+180
+***
+441
+()
+179
+***
+453
+()
+178
+***
+418
+()
+177
+***
+353
+()
+176
+***
+422
+()
+175
+***
+225
+***
+255
+()
+174
+***
+269
+()
+173
+***
+214
+()
+172
+***
+186
+()
+171
+***
+447
+()
+170
+***
+270
+***
+306
+()
+169
+***
+336
+()
+168
+***
+285
+()
+165
+***
+249
+()
+146
+***
+154
+()
+143
+***
+334
+()
+142
+***
+216
+***
+257
+()
+141
+***
+167
+***
+251
+()
+140
+***
+162
+***
+293
+()
+139
+***
+158
+()
+137
+***
+166
+***
+201
+()
+136
+***
+160
+()
+134
+***
+221
+()
+132
+***
+213
+()
+131
+***
+187
+()
+129
+***
+235
+()
+128
+***
+153
+()
+127
+***
+156
+()
+126
+***
+159
+***
+218
+()
+125
+***
+155
+()
+124
+***
+157
+()
+123
+***
+152
+()
+116
+***
+135
+***
+163
+()
+115
+***
+133
+***
+204
+***
+248
+()
+114
+***
+192
+***
+212
+()
+113
+***
+268
+()
+112
+***
+367
+()
+111
+***
+272
+()
+110
+***
+434
+()
+109
+***
+323
+()
+108
+***
+281
+()
+107
+***
+144
+***
+148
+()
+106
+***
+275
+()
+105
+***
+196
+***
+254
+()
+104
+***
+138
+***
+161
+()
+103
+***
+310
+()
+102
+***
+223
+***
+252
+()
+80
+()
+70
+()
+69
+()
+68
+()
+66
+()
+64
+()
+62
+***
+256
+()
+61
+***
+93
+()
+59
+***
+120
+()
+58
+()
+57
+***
+183
+()
+55
+()
+54
+()
+52
+***
+147
+()
+51
+***
+118
+()
+50
+***
+83
+()
+49
+***
+98
+()
+48
+***
+99
+()
+47
+()
+46
+***
+184
+()
+45
+***
+121
+()
+44
+()
+43
+***
+88
+()
+42
+***
+122
+()
+41
+***
+91
+()
+40
+***
+96
+()
+38
+***
+100
+()
+37
+***
+149
+()
+36
+***
+74
+()
+35
+***
+258
+()
+34
+***
+151
+()
+33
+***
+85
+()
+32
+()
+31
+***
+94
+()
+30
+***
+97
+()
+29
+***
+90
+()
+28
+***
+89
+()
+27
+***
+92
+()
+26
+***
+72
+***
+247
+()
+25
+***
+86
+()
+24
+***
+82
+()
+23
+***
+87
+***
+117
+()
+22
+***
+76
+***
+119
+()
+21
+***
+84
+()
+20
+***
+78
+()
+19
+***
+73
+()
+18
+***
+81
+()
+17
+***
+65
+()
+16
+***
+63
+***
+101
+()
+15
+***
+71
+()
+14
+***
+75
+()
+13
+***
+322
+()
+12
+***
+77
+()
+11
+***
+283
+()
+10
+***
+79
+()
+9
+***
+145
+***
+150
+()
+8
+***
+67
+()
+7
+***
+60
+***
+231
+()
+6
+***
+56
+***
+234
+()
+5
+***
+164
+***
+202
+()
+4
+***
+53
+()
+3
+***
+130
+***
+185
+***
+200
+()
+2
+***
+205
+()
+1
+***
+39
+***
+95
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stderr b/tests/long/10.mcf/ref/x86/linux/simple-timing/stderr
new file mode 100755
index 000000000..72ba90ece
--- /dev/null
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stderr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+warn: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stdout b/tests/long/10.mcf/ref/x86/linux/simple-timing/stdout
new file mode 100755
index 000000000..70a595464
--- /dev/null
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stdout
@@ -0,0 +1,32 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov  7 2008 03:21:37
+M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5
+M5 commit date Thu Nov 06 23:13:50 2008 -0800
+M5 started Nov  8 2008 01:13:22
+M5 executing on tater
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+MCF SPEC version 1.6.I
+by  Andreas Loebel
+Copyright (c) 1998,1999   ZIB Berlin
+All Rights Reserved.
+
+nodes                      : 500
+active arcs                : 1905
+simplex iterations         : 1502
+flow value                 : 4990014995
+new implicit arcs          : 23867
+active arcs                : 25772
+simplex iterations         : 2663
+flow value                 : 3080014995
+checksum                   : 68389
+optimal
+Exiting @ tick 495387670000 because target called exit()