Regression: Update stats for cache changes.

--HG--
extra : convert_revision : 005672e722dec00cb4c38501b5189b4eb7515ca1

3 files changed, 131 insertions, 115 deletions

diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
index fe99eeeb9..5a68a6d2e 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -11,7 +11,7 @@ physmem=system.physmem
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
+children=dcache icache l2cache toL2Bus tracer workload
 clock=500
 cpu_id=0
 defer_registration=false
@@ -24,22 +24,22 @@ max_loads_any_thread=0
 phase=0
 progress_interval=0
 system=system
+tracer=system.cpu.tracer
 workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-adaptive_compression=false
 addr_range=0:18446744073709551615
 assoc=2
 block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=10
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -53,12 +53,10 @@ prefetch_serial_squash=false
 prefetch_use_cpu_id=true
 prefetcher_size=100
 prioritizeRequests=false
-protocol=Null
 repl=Null
 size=262144
 split=false
 split_size=0
-store_compressed=false
 subblock_size=0
 tgts_per_mshr=5
 trace_addr=0
@@ -69,16 +67,15 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.icache]
 type=BaseCache
-adaptive_compression=false
 addr_range=0:18446744073709551615
 assoc=2
 block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=10
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -92,12 +89,10 @@ prefetch_serial_squash=false
 prefetch_use_cpu_id=true
 prefetcher_size=100
 prioritizeRequests=false
-protocol=Null
 repl=Null
 size=131072
 split=false
 split_size=0
-store_compressed=false
 subblock_size=0
 tgts_per_mshr=5
 trace_addr=0
@@ -108,16 +103,15 @@ mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.l2cache]
 type=BaseCache
-adaptive_compression=false
 addr_range=0:18446744073709551615
 assoc=2
 block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
 hash_delay=1
 latency=10000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=10
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -131,12 +125,10 @@ prefetch_serial_squash=false
 prefetch_use_cpu_id=true
 prefetcher_size=100
 prioritizeRequests=false
-protocol=Null
 repl=Null
 size=2097152
 split=false
 split_size=0
-store_compressed=false
 subblock_size=0
 tgts_per_mshr=5
 trace_addr=0
@@ -154,6 +146,9 @@ responder_set=false
 width=64
 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 
+[system.cpu.tracer]
+type=ExeTracer
+
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
index 56d2d33b9..e657db2a6 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,43 +1,43 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 697152                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 155896                       # Number of bytes of host memory used
-host_seconds                                   349.77                       # Real time elapsed on the host
-host_tick_rate                             1027373651                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1064489                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202188                       # Number of bytes of host memory used
+host_seconds                                   229.07                       # Real time elapsed on the host
+host_tick_rate                             1583716497                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   243840172                       # Number of instructions simulated
-sim_seconds                                  0.359341                       # Number of seconds simulated
-sim_ticks                                359340764000                       # Number of ticks simulated
+sim_seconds                                  0.362779                       # Number of seconds simulated
+sim_ticks                                362778959000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           82219469                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 12000.343864                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11000.343864                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 13897.517462                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11897.517462                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               81326673                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    10713859000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency    12407648000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.010859                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses               892796                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   9821063000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency  10622056000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.010859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses          892796                       # number of ReadReq MSHR misses
 system.cpu.dcache.SwapReq_accesses               3886                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency        12500                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency        11500                       # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits                   3882                       # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency          50000                       # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate          0.001029                       # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses                    4                       # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency        46000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate     0.001029                       # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses               4                       # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_avg_miss_latency        25000                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency        23000                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits                   3878                       # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency         200000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate          0.002059                       # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses                    8                       # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency       184000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate     0.002059                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses               8                       # number of SwapReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          22901836                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 12623.899964                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11623.899964                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              22855133                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency     589574000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.002039                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses               46703                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency    542871000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.002039                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses          46703                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency        25000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency        23000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              22806941                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    2372375000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.004144                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses               94895                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   2182585000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.004144                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses          94895                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                 110.894471                       # Average number of references to valid blocks.
@@ -47,31 +47,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           105121305                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 12031.341172                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11031.341172                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               104181806                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     11303433000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.008937                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                939499                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 14964.217554                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 12964.217554                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               104133614                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     14780023000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.009396                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                987691                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  10363934000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.008937                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           939499                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency  12804641000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.009396                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           987691                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses          105121305                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 12031.341172                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11031.341172                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 14964.217554                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 12964.217554                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              104181806                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    11303433000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.008937                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               939499                       # number of overall misses
+system.cpu.dcache.overall_hits              104133614                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    14780023000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.009396                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses               987691                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  10363934000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.008937                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          939499                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency  12804641000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.009396                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          987691                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                 935407                       # number of replacements
 system.cpu.dcache.sampled_refs                 939503                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               3560.887601                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               3565.606162                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                104185688                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle           134116230000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle           134193588000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                    94807                       # number of writebacks
 system.cpu.icache.ReadReq_accesses          243840173                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 13993.174061                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12993.174061                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 24972.696246                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 22972.696246                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits              243839294                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       12300000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency       21951000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  879                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency     11421000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     20193000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             879                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses           243840173                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 13993.174061                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12993.174061                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 24972.696246                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 22972.696246                       # average overall mshr miss latency
 system.cpu.icache.demand_hits               243839294                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        12300000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency        21951000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000004                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   879                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     11421000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     20193000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses              879                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses          243840173                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 13993.174061                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12993.174061                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 24972.696246                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 22972.696246                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits              243839294                       # number of overall hits
-system.cpu.icache.overall_miss_latency       12300000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency       21951000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  879                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     11421000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     20193000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000004                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses             879                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -148,57 +148,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                     25                       # number of replacements
 system.cpu.icache.sampled_refs                    879                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                716.200092                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                716.749422                       # Cycle average of tags in use
 system.cpu.icache.total_refs                243839294                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses            940381                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        13000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_accesses           46707                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency        22000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        11000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency   1027554000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses             46707                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    513777000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses        46707                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses            893675                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency        22000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        11000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                924777                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency     202852000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.016593                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               15604                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    171644000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.016593                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          15604                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_hits                826023                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    1488344000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.075701                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               67652                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    744172000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.075701                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          67652                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses          48196                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency        22000                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        11000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency   1060312000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses            48196                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency    530156000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses        48196                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.Writeback_accesses           94807                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits               94807                       # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate              1                       # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses             94807                       # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate            1                       # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses        94807                       # number of Writeback MSHR misses
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                 65.341195                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                 48.779815                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             940381                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        13000                       # average overall miss latency
+system.cpu.l2cache.demand_accesses             940382                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency        22000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 924777                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      202852000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.016593                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                15604                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                 826023                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     2515898000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.121609                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses               114359                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    171644000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.016593                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses           15604                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   1257949000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.121609                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses          114359                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses           1035188                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        13000                       # average overall miss latency
+system.cpu.l2cache.overall_accesses            940382                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency        22000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits               1019584                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     202852000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.015074                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses               15604                       # number of overall misses
+system.cpu.l2cache.overall_hits                826023                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    2515898000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.121609                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses              114359                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    171644000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.015074                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses          15604                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   1257949000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.121609                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses         114359                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -210,15 +231,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued            0
 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                 15604                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                   829                       # number of replacements
+system.cpu.l2cache.sampled_refs                 11345                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             10833.027960                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1019584                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              8098.685225                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  553407                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                     359340764000                       # number of cpu cycles simulated
+system.cpu.numCycles                     362778959000                       # number of cpu cycles simulated
 system.cpu.num_insts                        243840172                       # Number of instructions executed
 system.cpu.num_refs                         105125191                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             428                       # Number of system calls
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
index 51a3ec215..c0328c6cb 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
@@ -21,9 +21,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jun 21 2007 21:15:48
-M5 started Fri Jun 22 02:01:52 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Aug 12 2007 12:23:15
+M5 started Sun Aug 12 16:47:12 2007
+M5 executing on zeep
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 359340764000 because target called exit()
+Exiting @ tick 362778959000 because target called exit()