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author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-01-25 17:19:50 +0000 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-01-25 17:19:50 +0000 |
commit | a17dbdf8834b84f05a8f5154a74ac819fe8adc7c (patch) | |
tree | 8761136c790b84e20d6df2e84207eca3c553984b /tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini | |
parent | bd55c9e2af7fd6c06af48a020c29cb33ba1ca3fc (diff) | |
download | gem5-a17dbdf8834b84f05a8f5154a74ac819fe8adc7c.tar.xz |
stats: Update stats for final tick and memory bandwidth patches
Diffstat (limited to 'tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini')
-rw-r--r-- | tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini index 8b55eca4f..cbe7d05b4 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -17,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU @@ -44,8 +47,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[2] -icache_port=system.membus.port[1] +dcache_port=system.membus.port[3] +icache_port=system.membus.port[2] [system.cpu.dtb] type=ArmTLB @@ -61,7 +64,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic egid=100 env= errout=cerr @@ -85,7 +88,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory @@ -95,5 +98,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] |