tests: update stats for name changes

3 files changed, 16 insertions, 16 deletions

diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
index 75a3e24c1..1771ad8e9 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -164,14 +164,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/20.parser/ref/arm/linux/simple-timing/simout
index 697084dd6..3ee3b4f05 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 17:57:49
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 12:55:52
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
index 3b54b12a7..218238666 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 577686                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 258200                       # Number of bytes of host memory used
-host_seconds                                   985.02                       # Real time elapsed on the host
-host_tick_rate                              733214267                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2210994                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 217324                       # Number of bytes of host memory used
+host_seconds                                   257.37                       # Real time elapsed on the host
+host_tick_rate                             2806251427                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   569034848                       # Number of instructions simulated
 sim_seconds                                  0.722234                       # Number of seconds simulated
@@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses          1138918                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.992551                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4065.490059                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.992551                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          177979623                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 22417.457622                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622                       # average overall mshr miss latency
@@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses            11521                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.480677                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            984.426148                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.480677                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          516611385                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 24743.338252                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252                       # average overall mshr miss latency
@@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses          231204                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.178502                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.445374                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          5849.157602                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         14594.006011                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.178502                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.445374                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses           1150439                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -264,6 +264,6 @@ system.cpu.num_int_register_writes          425113002                       # nu
 system.cpu.num_load_insts                   126029556                       # Number of load instructions
 system.cpu.num_mem_refs                     182890035                       # number of memory refs
 system.cpu.num_store_insts                   56860479                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             548                       # Number of system calls
+system.cpu.workload.num_syscalls                  548                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------