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authorAli Saidi <Ali.Saidi@ARM.com>2011-08-19 15:08:08 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2011-08-19 15:08:08 -0500
commit999cd8aef5dfa3c22b02b55420608fbb8d7e7822 (patch)
tree98f11453678ed2be66b2ae3239b0ee42ad6f4e05 /tests/long/20.parser/ref/arm/linux
parentb94f84196924d60d4d4677929ddb6f677e3d96d9 (diff)
downloadgem5-999cd8aef5dfa3c22b02b55420608fbb8d7e7822.tar.xz
StoreSet: Update stats for store-set clearing
Diffstat (limited to 'tests/long/20.parser/ref/arm/linux')
-rw-r--r--tests/long/20.parser/ref/arm/linux/o3-timing/config.ini5
-rwxr-xr-xtests/long/20.parser/ref/arm/linux/o3-timing/simout10
-rw-r--r--tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt814
3 files changed, 416 insertions, 413 deletions
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
index da98ab03d..0b5a9f54e 100644
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -102,6 +102,7 @@ smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
+store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -499,9 +500,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
+executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/parser
gid=100
-input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/arm/scratch/sysexplr/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout
index 6f903bc98..76519111d 100755
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 15 2011 18:02:03
-gem5 started Jul 16 2011 01:32:47
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Aug 17 2011 19:27:45
+gem5 started Aug 17 2011 19:29:05
+gem5 executing on nadc-0388
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -67,4 +69,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 298073533000 because target called exit()
+Exiting @ tick 279789017500 because target called exit()
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
index 2fcdf0e96..ce0258252 100644
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.298074 # Number of seconds simulated
-sim_ticks 298073533000 # Number of ticks simulated
+sim_seconds 0.279789 # Number of seconds simulated
+sim_ticks 279789017500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 55166 # Simulator instruction rate (inst/s)
-host_tick_rate 28679876 # Simulator tick rate (ticks/s)
-host_mem_usage 269720 # Number of bytes of host memory used
-host_seconds 10393.12 # Real time elapsed on the host
-sim_insts 573342447 # Number of instructions simulated
+host_inst_rate 82238 # Simulator instruction rate (inst/s)
+host_tick_rate 40132128 # Simulator tick rate (ticks/s)
+host_mem_usage 268396 # Number of bytes of host memory used
+host_seconds 6971.70 # Real time elapsed on the host
+sim_insts 573340737 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -51,299 +51,299 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 596147067 # number of cpu cycles simulated
+system.cpu.numCycles 559578036 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 233829808 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 186147170 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 18448610 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 196945817 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 163449853 # Number of BTB hits
+system.cpu.BPredUnit.lookups 229313741 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 182941703 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 18381450 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 193404656 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 160578997 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 12453913 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 2627969 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 162380426 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1034385613 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 233829808 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 175903766 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 266887423 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 82201728 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 101000880 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 4224 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 119559 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 149451578 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 4693812 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 591651753 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.074862 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.819629 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 11881056 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 2583910 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 158920845 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1008979483 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 229313741 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 172460053 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 261292498 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 78073694 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 78434846 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 86 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 74310 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 146143180 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 4810109 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 555823153 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.154722 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.836930 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 324776586 54.89% 54.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 24968353 4.22% 59.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 42079547 7.11% 66.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 41036258 6.94% 73.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 43058687 7.28% 80.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 15845137 2.68% 83.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 19209353 3.25% 86.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 16779568 2.84% 89.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 63898264 10.80% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 294542931 52.99% 52.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 24434943 4.40% 57.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 41500058 7.47% 64.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 40458286 7.28% 72.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 42543437 7.65% 79.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 15388331 2.77% 82.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 18846128 3.39% 85.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 16230001 2.92% 88.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 61879038 11.13% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 591651753 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.392235 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.735118 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 182259766 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 93638385 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 246087836 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 8499427 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 61166339 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 34309417 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 95729 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 1169323827 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 222317 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 61166339 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 199917017 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 12999514 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 52654373 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 236541446 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 28373064 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 1103035585 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 553 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 9425467 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 15260638 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 2023 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 1222978410 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 4879529633 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 4879526297 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 3336 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 672201352 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 550777016 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2758214 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2758162 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 72689740 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 205506720 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 126653600 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 67829085 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 74819363 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 969401999 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 4509720 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 756022991 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1531556 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 398123182 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1180507714 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 631817 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 591651753 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.277818 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.523431 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 555823153 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.409798 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.803108 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 176155270 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 73642136 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 243542004 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 5471546 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 57012197 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 33378674 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 103333 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 1139235628 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 221531 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 57012197 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 192762447 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 6395244 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52127193 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 232252715 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 15273357 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 1073234487 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1226 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2982497 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 8850274 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 56 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 1193556306 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 4743331903 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 4743328950 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 2953 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 672198616 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 521357685 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2768330 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2768349 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 48304499 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 196270626 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 121806649 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 17302899 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 13929275 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 937590667 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 4537458 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 765577672 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 3452362 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 365845767 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1020513301 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 659897 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 555823153 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.377376 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.646867 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 262870171 44.43% 44.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 115951413 19.60% 64.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 93032822 15.72% 79.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 60874777 10.29% 90.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 37273328 6.30% 96.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 12385550 2.09% 98.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 5290297 0.89% 99.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3168401 0.54% 99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 804994 0.14% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 247650578 44.56% 44.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 96155335 17.30% 61.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 83204777 14.97% 76.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 61794788 11.12% 87.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 37799799 6.80% 94.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 16279306 2.93% 97.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 7068984 1.27% 98.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 4337899 0.78% 99.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1531687 0.28% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 591651753 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 555823153 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 275664 3.50% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 5340824 67.91% 71.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2248514 28.59% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 140807 1.12% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 6799143 54.23% 55.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 5597920 44.65% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 517172409 68.41% 68.41% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 381200 0.05% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 134 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.46% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 168107388 22.24% 90.69% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 70361857 9.31% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 513475935 67.07% 67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 381036 0.05% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 132 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.12% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 171848719 22.45% 89.57% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 79871847 10.43% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 756022991 # Type of FU issued
-system.cpu.iq.rate 1.268182 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 7865002 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010403 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 2113093981 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 1372453088 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 706634766 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 304 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 520 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 765577672 # Type of FU issued
+system.cpu.iq.rate 1.368134 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 12537870 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.016377 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 2102968429 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 1308573624 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 707132694 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 300 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 418 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 763887839 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 154 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 6326745 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 778115390 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 152 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 8455252 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 78733524 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 32052 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 425394 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 69049484 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 69497780 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 53390 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 614044 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 64202883 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 27275 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 239 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 28348 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 333 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 61166339 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 3065417 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 178437 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 983562638 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 12157762 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 205506720 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 126653600 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2737845 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 99480 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 4232 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 425394 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 18747710 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 6190012 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 24937722 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 730148660 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 160105072 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 25874323 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 57012197 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2686334 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 121984 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 951489929 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 12656652 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 196270626 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 121806649 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2752356 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 48623 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 7315 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 614044 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 18618092 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 6141777 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 24759869 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 733934042 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 162731362 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 31643630 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 9650919 # number of nop insts executed
-system.cpu.iew.exec_refs 226764096 # number of memory reference insts executed
-system.cpu.iew.exec_branches 149136596 # Number of branches executed
-system.cpu.iew.exec_stores 66659024 # Number of stores executed
-system.cpu.iew.exec_rate 1.224779 # Inst execution rate
-system.cpu.iew.wb_sent 718776639 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 706634782 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 402647843 # num instructions producing a value
-system.cpu.iew.wb_consumers 726069262 # num instructions consuming a value
+system.cpu.iew.exec_nop 9361804 # number of nop insts executed
+system.cpu.iew.exec_refs 234660567 # number of memory reference insts executed
+system.cpu.iew.exec_branches 147664615 # Number of branches executed
+system.cpu.iew.exec_stores 71929205 # Number of stores executed
+system.cpu.iew.exec_rate 1.311585 # Inst execution rate
+system.cpu.iew.wb_sent 721950956 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 707132710 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 399859111 # num instructions producing a value
+system.cpu.iew.wb_consumers 707515910 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.185336 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.554558 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.263689 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.565159 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 574686331 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 408895774 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 3877903 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 20690983 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 530485415 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.083322 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.748938 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 574684621 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 376818510 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 3877561 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 20574438 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 498810957 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.152109 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.870885 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 277701641 52.35% 52.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 135265417 25.50% 77.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 46444883 8.76% 86.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 21050080 3.97% 90.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 18829655 3.55% 94.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7074631 1.33% 95.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 8453874 1.59% 97.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3355983 0.63% 97.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 12309251 2.32% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 264965751 53.12% 53.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 115315817 23.12% 76.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 44565199 8.93% 85.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 20246779 4.06% 89.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 19896261 3.99% 93.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7328254 1.47% 94.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 7611881 1.53% 96.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3447651 0.69% 96.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 15433364 3.09% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 530485415 # Number of insts commited each cycle
-system.cpu.commit.count 574686331 # Number of instructions committed
+system.cpu.commit.committed_per_cycle::total 498810957 # Number of insts commited each cycle
+system.cpu.commit.count 574684621 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 184377295 # Number of memory references committed
-system.cpu.commit.loads 126773187 # Number of loads committed
+system.cpu.commit.refs 184376611 # Number of memory references committed
+system.cpu.commit.loads 126772845 # Number of loads committed
system.cpu.commit.membars 1488542 # Number of memory barriers committed
-system.cpu.commit.branches 120192372 # Number of branches committed
+system.cpu.commit.branches 120192030 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 473702225 # Number of committed integer instructions.
+system.cpu.commit.int_insts 473700857 # Number of committed integer instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 12309251 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 15433364 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1501751131 # The number of ROB reads
-system.cpu.rob.rob_writes 2028662566 # The number of ROB writes
-system.cpu.timesIdled 111416 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 4495314 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 573342447 # Number of Instructions Simulated
-system.cpu.committedInsts_total 573342447 # Number of Instructions Simulated
-system.cpu.cpi 1.039775 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.039775 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.961747 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.961747 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3357392406 # number of integer regfile reads
-system.cpu.int_regfile_writes 822350092 # number of integer regfile writes
+system.cpu.rob.rob_reads 1434873586 # The number of ROB reads
+system.cpu.rob.rob_writes 1960359919 # The number of ROB writes
+system.cpu.timesIdled 94610 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 3754883 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 573340737 # Number of Instructions Simulated
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@@ -352,146 +352,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
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-system.cpu.l2cache.ReadExReq_avg_miss_latency 34252.155692 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34223.974419 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34223.974419 # average overall miss latency
+system.cpu.l2cache.replacements 218713 # number of replacements
+system.cpu.l2cache.tagsinuse 21078.689035 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1567898 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 239082 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 6.557993 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 207809197000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 7685.698304 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 13392.990732 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.234549 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.408722 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 760512 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 1079434 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits 60 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits 232403 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 992915 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 992915 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 130232 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses 107668 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 237900 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 237900 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 4454609000 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 68500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 3687681000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 8142290000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 8142290000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 890744 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 1079434 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses 88 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 340071 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 1230815 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 1230815 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.146206 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate 0.318182 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.316604 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.193287 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.193287 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34205.179986 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 2446.428571 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34250.482966 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34225.683060 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34225.683060 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -500,32 +500,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 171107 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits 21 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits 21 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 21 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 130112 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses 466 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 107854 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 237966 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 237966 # number of overall MSHR misses
+system.cpu.l2cache.writebacks 171082 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 22 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 130210 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses
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+system.cpu.l2cache.demand_mshr_misses 237878 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 237878 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 4038190500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14451000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 3344342000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 7382532500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 7382532500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 4042910500 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146265 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.291068 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317993 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.193668 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.193668 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31036.264910 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31010.729614 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31008.047917 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31023.476043 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31023.476043 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146181 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.318182 # mshr miss rate for UpgradeReq accesses
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+system.cpu.l2cache.demand_mshr_miss_rate 0.193269 # mshr miss rate for demand accesses
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31049.155211 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency 31029.367995 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions