diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
| commit | 13a15c55a40e86e5f3948a387fb5e50b9a1cdccf (patch) | |
| tree | 762286677b3170cf9a7fb348f44e74a276230d6c /tests/long/20.parser/ref/arm | |
| parent | e9185363804489ce2b84d50fe77ed94f3a5f1e01 (diff) | |
| download | gem5-13a15c55a40e86e5f3948a387fb5e50b9a1cdccf.tar.xz | |
stats: update stats for previous cset
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
Diffstat (limited to 'tests/long/20.parser/ref/arm')
3 files changed, 93 insertions, 104 deletions
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini index 003dd533c..77998b688 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini @@ -157,9 +157,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/20.parser/ref/arm/linux/simple-timing/simout index 73953840b..063172b08 100755 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing/simout -Redirecting stderr to build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:52:30 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:57:01 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:50 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:07:44 +M5 executing on phenom command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -74,4 +72,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 745672616000 because target called exit() +Exiting @ tick 719872424000 because target called exit() diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt index 24713e5f3..6c09813e2 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1125820 # Simulator instruction rate (inst/s) -host_mem_usage 214880 # Number of bytes of host memory used -host_seconds 496.95 # Real time elapsed on the host -host_tick_rate 1500512692 # Simulator tick rate (ticks/s) +host_inst_rate 1404297 # Simulator instruction rate (inst/s) +host_mem_usage 200728 # Number of bytes of host memory used +host_seconds 398.40 # Real time elapsed on the host +host_tick_rate 1806912378 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 559470527 # Number of instructions simulated -sim_seconds 0.745673 # Number of seconds simulated -sim_ticks 745672616000 # Number of ticks simulated +sim_seconds 0.719872 # Number of seconds simulated +sim_ticks 719872424000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 127326326 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 20914.908888 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17914.908888 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 19806.811274 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16806.811274 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 126543330 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 16376290000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 15508654000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.006150 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 782996 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14027302000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 13159666000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.006150 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 782996 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 55727847 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 53833.507889 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50833.507889 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 55072849 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 35260840000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.011754 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 654998 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 33295846000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011754 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 654998 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 28149.273084 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25149.273084 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 55371547 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 10029586000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.006394 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 356300 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 8960686000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006394 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 356300 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 159.673059 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 183054173 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35909.141485 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 32909.141485 # average overall mshr miss latency -system.cpu.dcache.demand_hits 181616179 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 51637130000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.007856 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1437994 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 22415.807657 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19415.807657 # average overall mshr miss latency +system.cpu.dcache.demand_hits 181914877 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 25538240000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.006224 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1139296 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 47323148000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.007856 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1437994 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 22120352000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006224 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1139296 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.992972 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4067.215006 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.992721 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4066.183353 # Average occupied blocks per context system.cpu.dcache.overall_accesses 183054173 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35909.141485 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 32909.141485 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 22415.807657 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19415.807657 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 181616179 # number of overall hits -system.cpu.dcache.overall_miss_latency 51637130000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.007856 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1437994 # number of overall misses +system.cpu.dcache.overall_hits 181914877 # number of overall hits +system.cpu.dcache.overall_miss_latency 25538240000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.006224 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1139296 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 47323148000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.007856 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1437994 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 22120352000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006224 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1139296 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 1135200 # number of replacements system.cpu.dcache.sampled_refs 1139296 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4067.215006 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4066.183353 # Cycle average of tags in use system.cpu.dcache.total_refs 181914877 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 11578483000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 808512 # number of writebacks +system.cpu.dcache.writebacks 1025629 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 11521 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.485313 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 993.921198 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.482234 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 987.615046 # Average occupied blocks per context system.cpu.icache.overall_accesses 512145761 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency @@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 9788 # number of replacements system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 993.921198 # Cycle average of tags in use +system.cpu.icache.tagsinuse 987.615046 # Cycle average of tags in use system.cpu.icache.total_refs 512134240 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -150,37 +150,28 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 356300 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 33786 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 16770728000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.905175 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 322514 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 12900560000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.905175 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 322514 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 236267 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 6241716000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.336887 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 120033 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336887 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 120033 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 794517 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 662657 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 6856720000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.165962 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 131860 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 5274400000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165962 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 131860 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 298698 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51993.732800 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 15530424000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 298698 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11947920000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 298698 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 808512 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 808512 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 683315 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 5782504000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.139962 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 111202 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 4448080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139962 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 111202 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 1025629 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1025629 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.737661 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 6.147006 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 1150817 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 696443 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 23627448000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.394827 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 454374 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 919582 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 12024220000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.200931 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 231235 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 18174960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.394827 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 454374 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 9249400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.200931 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 231235 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.184240 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.380639 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 6037.178832 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 12472.788257 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.178887 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.445562 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 5861.784368 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14600.161549 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 1150817 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 696443 # number of overall hits -system.cpu.l2cache.overall_miss_latency 23627448000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.394827 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 454374 # number of overall misses +system.cpu.l2cache.overall_hits 919582 # number of overall hits +system.cpu.l2cache.overall_miss_latency 12024220000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.200931 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 231235 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 18174960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.394827 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 454374 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 9249400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.200931 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 231235 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 232496 # number of replacements -system.cpu.l2cache.sampled_refs 251560 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 212119 # number of replacements +system.cpu.l2cache.sampled_refs 232160 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18509.967089 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1191806 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 525324932000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 186433 # number of writebacks +system.cpu.l2cache.tagsinuse 20461.945917 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1427089 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 510281834000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 172310 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1491345232 # number of cpu cycles simulated +system.cpu.numCycles 1439744848 # number of cpu cycles simulated system.cpu.num_insts 559470527 # Number of instructions executed system.cpu.num_refs 184987503 # Number of memory references system.cpu.workload.PROG:num_syscalls 548 # Number of system calls |