tests: updates for stat name change

2 files changed, 16 insertions, 16 deletions

diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout
index 092b47dee..b82973c4c 100755
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:52:10
+M5 compiled Apr 21 2011 12:05:01
+M5 started Apr 21 2011 14:20:25
 M5 executing on maize
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
index 8a2f1e243..c47be9104 100644
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 191028                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 221120                       # Number of bytes of host memory used
-host_seconds                                  3001.36                       # Real time elapsed on the host
-host_tick_rate                              110860138                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 116803                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 223612                       # Number of bytes of host memory used
+host_seconds                                  4908.63                       # Real time elapsed on the host
+host_tick_rate                               67784916                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   573342397                       # Number of instructions simulated
 sim_seconds                                  0.332731                       # Number of seconds simulated
@@ -265,16 +265,16 @@ system.cpu.iew.iewIdleCycles                        0                       # Nu
 system.cpu.iew.iewLSQFullEvents                  7156                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.iewSquashCycles               57332647                       # Number of cycles IEW is squashing
 system.cpu.iew.iewUnblockCycles                209223                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked           75                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads         5626597                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses        13730                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation       241250                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads        24511                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads     70118828                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores     56769769                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.cacheBlocked            75                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.forwLoads          5626597                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.ignoredResponses        13730                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.memOrderViolation       241250                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.rescheduledLoads        24511                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.squashedLoads     70118828                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedStores     56769769                       # Number of stores squashed
 system.cpu.iew.memOrderViolationEvents         241250                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect      6965983                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect       18134157                       # Number of branches that were predicted taken incorrectly