diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:25 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:25 -0500 |
| commit | 1114be4b78c0855d96004b9f71c61d4b6a050d3a (patch) | |
| tree | eb1e2047d27bd31626530cae97cd9224e1dbbb11 /tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt | |
| parent | 7dde557fdc51140988092962137e1006d1609bea (diff) | |
| download | gem5-1114be4b78c0855d96004b9f71c61d4b6a050d3a.tar.xz | |
O3: Update stats for memory order violation checking patch.
Diffstat (limited to 'tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt | 774 |
1 files changed, 387 insertions, 387 deletions
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt index f8e3db8bb..0fc55f229 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,475 +1,475 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 189714 # Simulator instruction rate (inst/s) -host_mem_usage 264736 # Number of bytes of host memory used -host_seconds 8051.48 # Real time elapsed on the host -host_tick_rate 75880827 # Simulator tick rate (ticks/s) +host_inst_rate 135575 # Simulator instruction rate (inst/s) +host_mem_usage 259672 # Number of bytes of host memory used +host_seconds 11277.84 # Real time elapsed on the host +host_tick_rate 51792019 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1527476062 # Number of instructions simulated -sim_seconds 0.610953 # Number of seconds simulated -sim_ticks 610952992000 # Number of ticks simulated +sim_insts 1528988756 # Number of instructions simulated +sim_seconds 0.584102 # Number of seconds simulated +sim_ticks 584102039000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 220273443 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 239822696 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 218742072 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 237579384 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 16691862 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 254901320 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 254901320 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 16731555 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 252612909 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 252612909 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 149616585 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 33918821 # number cycles where commit BW limit reached +system.cpu.commit.COM:branches 149758588 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 41097639 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1083369873 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.409930 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.877801 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1035309655 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.476842 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.993609 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 454928288 41.99% 41.99% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 282557908 26.08% 68.07% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 120287774 11.10% 79.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 105365409 9.73% 88.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 40172301 3.71% 92.61% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 27676804 2.55% 95.16% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 11415389 1.05% 96.22% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 7047179 0.65% 96.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 33918821 3.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 433213212 41.84% 41.84% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 271303976 26.21% 68.05% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 102660477 9.92% 77.96% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 102477093 9.90% 87.86% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 38291141 3.70% 91.56% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 25044351 2.42% 93.98% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 10787246 1.04% 95.02% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 10434520 1.01% 96.03% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 41097639 3.97% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1083369873 # Number of insts commited each cycle -system.cpu.commit.COM:count 1527476062 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 1035309655 # Number of insts commited each cycle +system.cpu.commit.COM:count 1528988756 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu.commit.COM:int_insts 1526804920 # Number of committed integer instructions. -system.cpu.commit.COM:loads 383724495 # Number of loads committed +system.cpu.commit.COM:int_insts 1528317614 # Number of committed integer instructions. +system.cpu.commit.COM:loads 384102160 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 532790180 # Number of memory references committed +system.cpu.commit.COM:refs 533262345 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 16726957 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1527476062 # The number of committed instructions +system.cpu.commit.branchMispredicts 16763223 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 841443918 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1527476062 # Number of Instructions Simulated -system.cpu.committedInsts_total 1527476062 # Number of Instructions Simulated -system.cpu.cpi 0.799951 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.799951 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 320046346 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 15794.070061 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8150.695480 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 317137092 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 45948961500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.009090 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 2909254 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 1183970 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 14062264500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005391 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1725284 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 149065701 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 23554.108597 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18051.470496 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 147419835 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 38766906500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.011041 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1645866 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 608291 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 18729754500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006961 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1037575 # number of WriteReq MSHR misses +system.cpu.commit.commitSquashedInsts 795955462 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1528988756 # Number of Instructions Simulated +system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated +system.cpu.cpi 0.764037 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.764037 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 323639192 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 15916.826695 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8444.942006 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 320628262 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 47924451000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.009303 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 3010930 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 1248670 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 14882183500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005445 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1762260 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 23726.182533 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18050.899847 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 147539972 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 38441849000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.010862 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1620229 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 607112 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 18287673500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006792 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1013117 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 185.704246 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 185.317160 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 469112047 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18597.944291 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 11868.871701 # average overall mshr miss latency -system.cpu.dcache.demand_hits 464556927 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 84715868000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.009710 # miss rate for demand accesses -system.cpu.dcache.demand_misses 4555120 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1792261 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 32792019000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005890 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2762859 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 472799393 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 18648.960228 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11951.477943 # average overall mshr miss latency +system.cpu.dcache.demand_hits 468168234 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 86366300000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.009795 # miss rate for demand accesses +system.cpu.dcache.demand_misses 4631159 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1855782 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 33169857000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005870 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2775377 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.998028 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4087.922333 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 469112047 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18597.944291 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 11868.871701 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.998173 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4088.515779 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 472799393 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 18648.960228 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11951.477943 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 464556927 # number of overall hits -system.cpu.dcache.overall_miss_latency 84715868000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.009710 # miss rate for overall accesses -system.cpu.dcache.overall_misses 4555120 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1792261 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 32792019000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005890 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2762859 # number of overall MSHR misses +system.cpu.dcache.overall_hits 468168234 # number of overall hits +system.cpu.dcache.overall_miss_latency 86366300000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.009795 # miss rate for overall accesses +system.cpu.dcache.overall_misses 4631159 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1855782 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 33169857000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005870 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2775377 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2504740 # number of replacements -system.cpu.dcache.sampled_refs 2508836 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2529347 # number of replacements +system.cpu.dcache.sampled_refs 2533443 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4087.922333 # Cycle average of tags in use -system.cpu.dcache.total_refs 465901497 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 2529382000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2229751 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 215366555 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 2516935544 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 437043857 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 404205746 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 113949773 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 26753715 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 254901320 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 190461812 # Number of cache lines fetched -system.cpu.fetch.Cycles 445534669 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 3068431 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1374706338 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 85274 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 18549281 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.208610 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 190461812 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 220273443 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.125051 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1197319646 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.144693 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.178811 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4088.515779 # Cycle average of tags in use +system.cpu.dcache.total_refs 469490463 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 2268948000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2231104 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 187291575 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 2489806075 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 422005844 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 404270583 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 108207267 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 21741653 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 252612909 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 188594062 # Number of cache lines fetched +system.cpu.fetch.Cycles 440470513 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 3788635 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 1360923556 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 78504 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 19199509 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.216240 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 188594062 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 218742072 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.164971 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1143516922 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.221243 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.208291 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 756027205 63.14% 63.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 34054494 2.84% 65.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 36745231 3.07% 69.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33767076 2.82% 71.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21459245 1.79% 73.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 40493114 3.38% 77.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 45860411 3.83% 80.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 35731624 2.98% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 193181246 16.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 707206433 61.84% 61.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32665502 2.86% 64.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37223305 3.26% 67.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33654778 2.94% 70.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21116720 1.85% 72.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 40194771 3.52% 76.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 44517058 3.89% 80.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 36097891 3.16% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 190840464 16.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1197319646 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 31 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 190461812 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 6527.954910 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3419.281975 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 190192396 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1758735500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.001415 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 269416 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1570 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 915841000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.001406 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 267846 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 1143516922 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 40 # number of floating regfile reads +system.cpu.icache.ReadReq_accesses 188594062 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 6510.591789 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3406.338578 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 188336504 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1676855000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.001366 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 257558 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1428 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 872465500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.001358 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 256130 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 17699.832480 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 16890.533363 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 190461812 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 6527.954910 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3419.281975 # average overall mshr miss latency -system.cpu.icache.demand_hits 190192396 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1758735500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.001415 # miss rate for demand accesses -system.cpu.icache.demand_misses 269416 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1570 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 915841000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.001406 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 267846 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 188594062 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 6510.591789 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3406.338578 # average overall mshr miss latency +system.cpu.icache.demand_hits 188336504 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1676855000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.001366 # miss rate for demand accesses +system.cpu.icache.demand_misses 257558 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1428 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 872465500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.001358 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 256130 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.466021 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 954.411836 # Average occupied blocks per context -system.cpu.icache.overall_accesses 190461812 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 6527.954910 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3419.281975 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.469099 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 960.715295 # Average occupied blocks per context +system.cpu.icache.overall_accesses 188594062 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 6510.591789 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3406.338578 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 190192396 # number of overall hits -system.cpu.icache.overall_miss_latency 1758735500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.001415 # miss rate for overall accesses -system.cpu.icache.overall_misses 269416 # number of overall misses -system.cpu.icache.overall_mshr_hits 1570 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 915841000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.001406 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 267846 # number of overall MSHR misses +system.cpu.icache.overall_hits 188336504 # number of overall hits +system.cpu.icache.overall_miss_latency 1676855000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.001366 # miss rate for overall accesses +system.cpu.icache.overall_misses 257558 # number of overall misses +system.cpu.icache.overall_mshr_hits 1428 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 872465500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.001358 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 256130 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 9298 # number of replacements -system.cpu.icache.sampled_refs 10745 # Sample count of references to valid blocks. +system.cpu.icache.replacements 9707 # number of replacements +system.cpu.icache.sampled_refs 11150 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 954.411836 # Cycle average of tags in use -system.cpu.icache.total_refs 190184700 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 960.715295 # Cycle average of tags in use +system.cpu.icache.total_refs 188329447 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 3 # number of writebacks -system.cpu.idleCycles 24586339 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 175611349 # Number of branches executed +system.cpu.icache.writebacks 6 # number of writebacks +system.cpu.idleCycles 24687157 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 173444431 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.537639 # Inst execution rate -system.cpu.iew.EXEC:refs 604612823 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 164362000 # Number of stores executed +system.cpu.iew.EXEC:rate 1.602205 # Inst execution rate +system.cpu.iew.EXEC:refs 612750445 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 165978925 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2150204737 # num instructions consuming a value -system.cpu.iew.WB:count 1865910107 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.666196 # average fanout of values written-back +system.cpu.iew.WB:consumers 2110704618 # num instructions consuming a value +system.cpu.iew.WB:count 1858331416 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.678632 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1432457554 # num instructions producing a value -system.cpu.iew.WB:rate 1.527049 # insts written-back per cycle -system.cpu.iew.WB:sent 1872952311 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 18187438 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 9702727 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 598780500 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 9848 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2427132 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 227725972 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2368916953 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 440250823 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 24902521 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1878850199 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 999062 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1432391344 # num instructions producing a value +system.cpu.iew.WB:rate 1.590759 # insts written-back per cycle +system.cpu.iew.WB:sent 1864643959 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 18167511 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9685611 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 586119276 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 9659 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2269927 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 223085364 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2324941378 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 446771520 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30325762 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1871702722 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 1004270 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 48995 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 113949773 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 1501929 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 42321 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 108207267 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1500742 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 119150872 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 153037 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 122021898 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 146459 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 1905759 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1230 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 215056005 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 78660287 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 1905759 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 2718790 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 15468648 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 3097184079 # number of integer regfile reads -system.cpu.int_regfile_writes 1741804464 # number of integer regfile writes -system.cpu.ipc 1.250077 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.250077 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2283854 0.12% 0.12% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1286143659 67.56% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 446588314 23.46% 91.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 168736893 8.86% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 2443893 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1254 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 202017116 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 73925179 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 2443893 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2771097 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 15396414 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 3111234049 # number of integer regfile reads +system.cpu.int_regfile_writes 1733847214 # number of integer regfile writes +system.cpu.ipc 1.308837 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.308837 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2348064 0.12% 0.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1272739342 66.91% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 456676516 24.01% 91.05% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 170264562 8.95% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1903752720 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 12019370 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.006314 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 1902028484 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 11137895 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.005856 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 1063366 8.85% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 7508013 62.47% 71.31% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 3447991 28.69% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1120921 10.06% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 10.06% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 7318318 65.71% 75.77% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 2698656 24.23% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1197319646 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.590012 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.576110 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1143516922 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.663315 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.649679 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 380569061 31.79% 31.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 297509781 24.85% 56.63% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 210374930 17.57% 74.20% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 147240856 12.30% 86.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 95168175 7.95% 94.45% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 42314918 3.53% 97.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 17818883 1.49% 99.47% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 5974413 0.50% 99.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 348629 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 363234856 31.76% 31.76% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 268152711 23.45% 55.21% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 190268701 16.64% 71.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 150184864 13.13% 84.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 96042571 8.40% 93.39% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 45507451 3.98% 97.37% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 20662852 1.81% 99.17% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 8604200 0.75% 99.92% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 858716 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1197319646 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.558019 # Inst issue rate -system.cpu.iq.fp_alu_accesses 59 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 119 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 7970 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 1913488177 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 5017400187 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 1865910076 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 3209512631 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 2368907105 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1903752720 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 9848 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 838752495 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 555850 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 9295 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1472780543 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 786848 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34255.494728 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.453653 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 539884 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 8459874000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.313865 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 246964 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7656243000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313865 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 246964 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1732679 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34171.480760 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.917505 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1415970 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 10822415500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.182786 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 316709 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 9818903000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.182786 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 316709 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 256943 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 40.077896 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.030576 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_hits 1216 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_miss_latency 10249000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 0.995267 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 255727 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7928312000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.995267 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 255727 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2229754 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2229754 # number of Writeback hits +system.cpu.iq.ISSUE:issued_per_cycle::total 1143516922 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.628165 # Inst issue rate +system.cpu.iq.fp_alu_accesses 77 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 156 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 40 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 7351 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 1910818238 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 4959453857 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1858331376 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 3120531509 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 2324931719 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1902028484 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 9659 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 793159883 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 742228 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 9106 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1353359987 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 775816 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34258.394889 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31002.535640 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 528344 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 8477993500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.318983 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 247472 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7672259500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.318983 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 247472 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1768657 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34159.791245 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.301453 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1429599 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 11582150500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.191704 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 339058 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 10512595500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191704 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 339058 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 244851 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 42.349749 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.844007 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_hits 1225 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_miss_latency 10317500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 0.994997 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 243626 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7553342500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994997 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 243626 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2231110 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2231110 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.404070 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 5.363240 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2519527 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34208.290090 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31002.276142 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1955854 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 19282289500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.223722 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 563673 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 2544473 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34201.394643 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.134486 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1957943 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 20060144000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.230511 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 586530 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 17475146000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.223722 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 563673 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 18184855000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.230511 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 586530 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.213694 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.433705 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 7002.339473 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14211.631717 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 2519527 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34208.290090 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31002.276142 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.236559 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.418198 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 7751.549385 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13703.522900 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 2544473 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34201.394643 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.134486 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1955854 # number of overall hits -system.cpu.l2cache.overall_miss_latency 19282289500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.223722 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 563673 # number of overall misses +system.cpu.l2cache.overall_hits 1957943 # number of overall hits +system.cpu.l2cache.overall_miss_latency 20060144000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.230511 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 586530 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 17475146000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.223722 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 563673 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 18184855000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.230511 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 586530 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 553099 # number of replacements -system.cpu.l2cache.sampled_refs 571950 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 575744 # number of replacements +system.cpu.l2cache.sampled_refs 594863 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 21213.971190 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3090858 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 329890014000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 404346 # number of writebacks -system.cpu.memDep0.conflictingLoads 432038121 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 167866970 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 598780500 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 227724252 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 1024928879 # number of misc regfile reads -system.cpu.numCycles 1221905985 # number of cpu cycles simulated +system.cpu.l2cache.tagsinuse 21455.072285 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3190393 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 306991433000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 412280 # number of writebacks +system.cpu.memDep0.conflictingLoads 354716110 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 139191834 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 586119276 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 223082546 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1024751398 # number of misc regfile reads +system.cpu.numCycles 1168204079 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 64472267 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1425688721 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 52544368 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 479786184 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 82632603 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 8428 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 5772028874 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2456264739 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2290118455 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 385614091 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 113949773 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 153477395 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 864429734 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 19762 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 5772009112 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 19936 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 2550 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 360051799 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 2561 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 3418371032 # The number of ROB reads -system.cpu.rob.rob_writes 4851844016 # The number of ROB writes -system.cpu.timesIdled 625791 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:BlockCycles 50725953 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1427299027 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 53866080 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 461056510 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 71664979 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 8215 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 5693696762 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2424853504 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2263021553 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 385257729 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 108207267 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 138255029 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 835722526 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 18042 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 5693678720 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 14434 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 2322 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 301380597 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 2286 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3319156234 # The number of ROB reads +system.cpu.rob.rob_writes 4758159890 # The number of ROB writes +system.cpu.timesIdled 639156 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- |