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authorLisa Hsu <Lisa.Hsu@amd.com>2010-02-25 10:08:41 -0800
committerLisa Hsu <Lisa.Hsu@amd.com>2010-02-25 10:08:41 -0800
commitee20a7c0bddf1f2a1913ddb176910bdce4c13b9c (patch)
tree93b9bd8be890468c550b85eae4b467285b4d6811 /tests/long/20.parser/ref/x86/linux/simple-timing
parent7f3cd9a9fd636c1e48dcec20de3f6c14214d0ce4 (diff)
downloadgem5-ee20a7c0bddf1f2a1913ddb176910bdce4c13b9c.tar.xz
stats: update stats for the changes I pushed re: shared cache occupancy
Diffstat (limited to 'tests/long/20.parser/ref/x86/linux/simple-timing')
-rw-r--r--tests/long/20.parser/ref/x86/linux/simple-timing/config.ini7
-rwxr-xr-xtests/long/20.parser/ref/x86/linux/simple-timing/simout8
-rw-r--r--tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt16
3 files changed, 21 insertions, 10 deletions
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
index a7ed66f8a..c8eb88a42 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -45,6 +45,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -79,6 +80,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -113,6 +115,7 @@ hash_delay=1
latency=10000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
@@ -154,9 +157,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/parser
gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
index a11db4e1e..458afbc15 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 8 2009 16:16:58
-M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff
-M5 started Nov 8 2009 16:39:28
-M5 executing on maize
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:54:07
+M5 executing on SC2B0619
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
index 0e665b6ef..87bf15b21 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1459378 # Simulator instruction rate (inst/s)
-host_mem_usage 198104 # Number of bytes of host memory used
-host_seconds 1024.89 # Real time elapsed on the host
-host_tick_rate 1680505604 # Simulator tick rate (ticks/s)
+host_inst_rate 925832 # Simulator instruction rate (inst/s)
+host_mem_usage 200280 # Number of bytes of host memory used
+host_seconds 1615.52 # Real time elapsed on the host
+host_tick_rate 1066115675 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495700470 # Number of instructions simulated
sim_seconds 1.722332 # Number of seconds simulated
@@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 3192703 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.997757 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4086.814341 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 533262382 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 38769.912986 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35769.912360 # average overall mshr miss latency
@@ -103,6 +105,8 @@ system.cpu.icache.demand_mshr_misses 2814 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.433368 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 887.538461 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1068347073 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 48626.865672 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 45626.865672 # average overall mshr miss latency
@@ -177,6 +181,10 @@ system.cpu.l2cache.demand_mshr_misses 1210961 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.111890 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.413414 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 3666.426168 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 13546.751396 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 2521227 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000.009497 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency