summaryrefslogtreecommitdiff
path: root/tests/long/20.parser/ref/x86/linux
diff options
context:
space:
mode:
authorSteve Reinhardt <stever@gmail.com>2009-02-16 12:09:45 -0500
committerSteve Reinhardt <stever@gmail.com>2009-02-16 12:09:45 -0500
commit89ea32325094665c16688212b5a2cd7b7bbf5f03 (patch)
tree2259a04ed0e6c700096d8f662726c51a2c6da525 /tests/long/20.parser/ref/x86/linux
parent89a7fb03934b3e38c7d8b2c4818794b3ec874fdf (diff)
downloadgem5-89ea32325094665c16688212b5a2cd7b7bbf5f03.tar.xz
Update stats for new prefetching fixes.
Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
Diffstat (limited to 'tests/long/20.parser/ref/x86/linux')
-rwxr-xr-xtests/long/20.parser/ref/x86/linux/simple-atomic/simout8
-rw-r--r--tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt8
-rw-r--r--tests/long/20.parser/ref/x86/linux/simple-timing/config.ini9
-rwxr-xr-xtests/long/20.parser/ref/x86/linux/simple-timing/simout8
-rw-r--r--tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt35
5 files changed, 19 insertions, 49 deletions
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
index 08a12f2a0..0154cb675 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 1 2009 00:35:14
-M5 revision ddc342563140 5849 default qtip upconfaultstats.patch tip qbase
-M5 started Feb 1 2009 01:31:23
-M5 executing on fajita
+M5 compiled Feb 16 2009 00:19:15
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 01:09:31
+M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py long/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
index 9ef20eecb..2072caa4b 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 942344 # Simulator instruction rate (inst/s)
-host_mem_usage 199592 # Number of bytes of host memory used
-host_seconds 1586.98 # Real time elapsed on the host
-host_tick_rate 547379933 # Simulator tick rate (ticks/s)
+host_inst_rate 1649324 # Simulator instruction rate (inst/s)
+host_mem_usage 201208 # Number of bytes of host memory used
+host_seconds 906.72 # Real time elapsed on the host
+host_tick_rate 958044415 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495482356 # Number of instructions simulated
sim_seconds 0.868682 # Number of seconds simulated
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
index 793578856..87163bbc2 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -46,12 +46,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@@ -83,12 +82,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@@ -120,12 +118,11 @@ latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
-prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
-prefetch_miss=false
+prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
index 3b8d98147..6d4d2b6e7 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 1 2009 00:35:14
-M5 revision ddc342563140 5849 default qtip upconfaultstats.patch tip qbase
-M5 started Feb 1 2009 01:51:40
-M5 executing on fajita
+M5 compiled Feb 16 2009 00:19:15
+M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
+M5 started Feb 16 2009 01:11:36
+M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py long/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
index c473a6423..923ce5951 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 856633 # Simulator instruction rate (inst/s)
-host_mem_usage 207060 # Number of bytes of host memory used
-host_seconds 1745.77 # Real time elapsed on the host
-host_tick_rate 1369809690 # Simulator tick rate (ticks/s)
+host_inst_rate 1421036 # Simulator instruction rate (inst/s)
+host_mem_usage 208620 # Number of bytes of host memory used
+host_seconds 1052.39 # Real time elapsed on the host
+host_tick_rate 2272325062 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495482356 # Number of instructions simulated
sim_seconds 2.391370 # Number of seconds simulated
@@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.005988 # ms
system.cpu.dcache.overall_mshr_misses 3192961 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 2513875 # number of replacements
system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@@ -126,15 +117,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000002 # ms
system.cpu.icache.overall_mshr_misses 2813 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 1253 # number of replacements
system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@@ -209,15 +191,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.480279 # m
system.cpu.l2cache.overall_mshr_misses 1210680 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 663512 # number of replacements
system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions