diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-10 09:59:01 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-10 09:59:01 -0600 |
| commit | a5a2b9ecbdeeefcfa8d5a5d116c385cdf59e0256 (patch) | |
| tree | 0d018e4f474bb9dd45bffad990de8e753114e6c2 /tests/long/20.parser/ref/x86/linux | |
| parent | acbc03ae464b027fe93dca3a0bc796ef63f53113 (diff) | |
| download | gem5-a5a2b9ecbdeeefcfa8d5a5d116c385cdf59e0256.tar.xz | |
X86 Regressions: Update stats due to fence instruction
Diffstat (limited to 'tests/long/20.parser/ref/x86/linux')
11 files changed, 591 insertions, 600 deletions
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini index 71df37b56..b2ef015f3 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini @@ -500,9 +500,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout index 7acfed5bd..f37768727 100755 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout @@ -3,11 +3,10 @@ Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 16 2011 11:08:03 -gem5 started Nov 17 2011 13:09:16 +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -tests Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -82,4 +81,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 494093841000 because target called exit() +Exiting @ tick 493912286000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt index 548cdcdb0..556f62c4f 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,149 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.494094 # Number of seconds simulated -sim_ticks 494093841000 # Number of ticks simulated +sim_seconds 0.493912 # Number of seconds simulated +sim_ticks 493912286000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111156 # Simulator instruction rate (inst/s) -host_tick_rate 35920075 # Simulator tick rate (ticks/s) -host_mem_usage 281020 # Number of bytes of host memory used -host_seconds 13755.37 # Real time elapsed on the host +host_inst_rate 108889 # Simulator instruction rate (inst/s) +host_tick_rate 35174673 # Simulator tick rate (ticks/s) +host_mem_usage 280548 # Number of bytes of host memory used +host_seconds 14041.70 # Real time elapsed on the host sim_insts 1528988756 # Number of instructions simulated system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 988187683 # number of cpu cycles simulated +system.cpu.numCycles 987824573 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 245753731 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 245753731 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16579058 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 236460078 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 218454939 # Number of BTB hits +system.cpu.BPredUnit.lookups 245766486 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 245766486 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16576996 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 236474058 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 218464201 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 205538766 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1343537923 # Number of instructions fetch has processed -system.cpu.fetch.Branches 245753731 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 218454939 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 436709904 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 120016352 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 218837683 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33103 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 345399 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 194719765 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4085375 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 964635983 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.598912 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.317298 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 205503020 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1343384866 # Number of instructions fetch has processed +system.cpu.fetch.Branches 245766486 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 218464201 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 436676837 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 119986236 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 218554807 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32387 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 341323 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 194710374 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4099618 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 964252463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.599701 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.317490 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 531979476 55.15% 55.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32383346 3.36% 58.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38813168 4.02% 62.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32534184 3.37% 65.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21860326 2.27% 68.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 36455994 3.78% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 49125826 5.09% 77.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 36953777 3.83% 80.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 184529886 19.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 531629837 55.13% 55.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32377332 3.36% 58.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38827894 4.03% 62.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32536894 3.37% 65.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21844251 2.27% 68.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 36448993 3.78% 71.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 49128972 5.10% 77.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 36937786 3.83% 80.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 184520504 19.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 964635983 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.248691 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.359598 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 264568111 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 174813294 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 373028079 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49055371 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 103171128 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2446190376 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 103171128 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 301809231 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40269862 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9996 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 383504038 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 135871728 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2393655047 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2663 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25553817 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 92121641 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2227336205 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5630423595 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5630180918 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 242677 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 964252463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.248796 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.359943 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 264509435 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 174554141 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 373011587 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49033211 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 103144089 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2445932072 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 103144089 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 301738657 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40282868 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12225 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 383467875 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 135606749 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2393375507 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2559 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25131978 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 92224846 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 8 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2227188673 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5629907069 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5629667957 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 239112 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 800037178 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1323 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1277 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 319257105 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 577954406 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 226554784 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 227345729 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 66055755 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2286934263 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 9822 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1922478378 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1310077 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 755451043 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1190251690 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 9269 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 964635983 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.992957 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.810982 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 799889646 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1309 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1288 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 318947403 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 577879232 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 226530900 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 227222440 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 65937432 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2286709085 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12489 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1922370305 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1306641 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 755226802 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1190125426 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 11936 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 964252463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.993638 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.811521 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 283040019 29.34% 29.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 160280005 16.62% 45.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 162996180 16.90% 62.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 148777682 15.42% 78.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 109013815 11.30% 89.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60046720 6.22% 95.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 30822079 3.20% 99.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 8624231 0.89% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1035252 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 282911384 29.34% 29.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 160280603 16.62% 45.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 162550496 16.86% 62.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 148847741 15.44% 78.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 109081156 11.31% 89.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60080329 6.23% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 30822605 3.20% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8641604 0.90% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1036545 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 964635983 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 964252463 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2243375 14.67% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9951583 65.07% 79.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3098283 20.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2246339 14.60% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 10026447 65.19% 79.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3108042 20.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2418078 0.13% 0.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1274783906 66.31% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2420122 0.13% 0.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1274712167 66.31% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued @@ -169,85 +169,85 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 463737726 24.12% 90.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 181538665 9.44% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 463703127 24.12% 90.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 181534884 9.44% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1922478378 # Type of FU issued -system.cpu.iq.rate 1.945459 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15293241 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007955 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4826191069 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3042585561 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1874784055 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4988 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82956 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1935351994 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1547 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 158191943 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1922370305 # Type of FU issued +system.cpu.iq.rate 1.946064 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15380828 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008001 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4825675637 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3042139517 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1874661917 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4905 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 81824 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 136 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1935329448 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1563 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 158391521 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 193852246 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 372238 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 283888 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 77394965 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 193777072 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 372742 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 283642 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77371112 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2343 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 34 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2379 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 103171128 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9041820 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1420232 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2286944085 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1121311 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 577954406 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 226555150 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6075 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1022506 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29752 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 283888 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15692203 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2347782 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18039985 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1889278448 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 454785721 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 33199930 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 103144089 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9045659 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1404502 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2286721574 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1118432 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 577879232 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 226531297 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6081 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1006586 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29974 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 283642 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15693422 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2344063 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18037485 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1889150749 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 454748002 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 33219556 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 629316980 # number of memory reference insts executed -system.cpu.iew.exec_branches 176731992 # Number of branches executed -system.cpu.iew.exec_stores 174531259 # Number of stores executed -system.cpu.iew.exec_rate 1.911862 # Inst execution rate -system.cpu.iew.wb_sent 1882655317 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1874784158 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1440755706 # num instructions producing a value -system.cpu.iew.wb_consumers 2135030641 # num instructions consuming a value +system.cpu.iew.exec_refs 629271939 # number of memory reference insts executed +system.cpu.iew.exec_branches 176719729 # Number of branches executed +system.cpu.iew.exec_stores 174523937 # Number of stores executed +system.cpu.iew.exec_rate 1.912435 # Inst execution rate +system.cpu.iew.wb_sent 1882531239 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1874662053 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1440606287 # num instructions producing a value +system.cpu.iew.wb_consumers 2134778201 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.897194 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.674817 # average fanout of values written-back +system.cpu.iew.wb_rate 1.897768 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.674827 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 757965703 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 757743569 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16607079 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 861464855 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.774871 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.287572 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16604349 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 861108374 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.775605 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.288022 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 338524013 39.30% 39.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 210779915 24.47% 63.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 75257513 8.74% 72.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92637954 10.75% 83.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34058407 3.95% 87.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27966548 3.25% 90.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15953506 1.85% 92.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12303443 1.43% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 53983556 6.27% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 338327816 39.29% 39.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 210551706 24.45% 63.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 75360819 8.75% 72.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92562974 10.75% 83.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34054041 3.95% 87.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27955182 3.25% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16032820 1.86% 92.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12266632 1.42% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 53996384 6.27% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 861464855 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 861108374 # Number of insts commited each cycle system.cpu.commit.count 1528988756 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 533262345 # Number of memory references committed @@ -257,49 +257,49 @@ system.cpu.commit.branches 149758588 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 53983556 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 53996384 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3094435758 # The number of ROB reads -system.cpu.rob.rob_writes 4677260376 # The number of ROB writes -system.cpu.timesIdled 606046 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 23551700 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3093844315 # The number of ROB reads +system.cpu.rob.rob_writes 4676786954 # The number of ROB writes +system.cpu.timesIdled 606516 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 23572110 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1528988756 # Number of Instructions Simulated system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated -system.cpu.cpi 0.646301 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.646301 # CPI: Total CPI of All Threads -system.cpu.ipc 1.547266 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.547266 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3179235417 # number of integer regfile reads -system.cpu.int_regfile_writes 1744932190 # number of integer regfile writes -system.cpu.fp_regfile_reads 109 # number of floating regfile reads -system.cpu.fp_regfile_writes 3 # number of floating regfile writes -system.cpu.misc_regfile_reads 1039364909 # number of misc regfile reads -system.cpu.icache.replacements 9996 # number of replacements -system.cpu.icache.tagsinuse 975.733254 # Cycle average of tags in use -system.cpu.icache.total_refs 194489021 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11497 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 16916.501783 # Average number of references to valid blocks. +system.cpu.cpi 0.646064 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.646064 # CPI: Total CPI of All Threads +system.cpu.ipc 1.547834 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.547834 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3179044858 # number of integer regfile reads +system.cpu.int_regfile_writes 1744829680 # number of integer regfile writes +system.cpu.fp_regfile_reads 145 # number of floating regfile reads +system.cpu.fp_regfile_writes 5 # number of floating regfile writes +system.cpu.misc_regfile_reads 1039286160 # number of misc regfile reads +system.cpu.icache.replacements 10045 # number of replacements +system.cpu.icache.tagsinuse 976.337758 # Cycle average of tags in use +system.cpu.icache.total_refs 194480398 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 11548 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 16841.045895 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 975.733254 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.476432 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 194495909 # number of ReadReq hits -system.cpu.icache.demand_hits 194495909 # number of demand (read+write) hits -system.cpu.icache.overall_hits 194495909 # number of overall hits -system.cpu.icache.ReadReq_misses 223856 # number of ReadReq misses -system.cpu.icache.demand_misses 223856 # number of demand (read+write) misses -system.cpu.icache.overall_misses 223856 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 1547338000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 1547338000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 1547338000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 194719765 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 194719765 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 194719765 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.001150 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.001150 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.001150 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 6912.202487 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 6912.202487 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 6912.202487 # average overall miss latency +system.cpu.icache.occ_blocks::0 976.337758 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.476727 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 194486608 # number of ReadReq hits +system.cpu.icache.demand_hits 194486608 # number of demand (read+write) hits +system.cpu.icache.overall_hits 194486608 # number of overall hits +system.cpu.icache.ReadReq_misses 223766 # number of ReadReq misses +system.cpu.icache.demand_misses 223766 # number of demand (read+write) misses +system.cpu.icache.overall_misses 223766 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 1539723000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 1539723000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 1539723000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 194710374 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 194710374 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 194710374 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.001149 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.001149 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.001149 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 6880.951530 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 6880.951530 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 6880.951530 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -309,136 +309,136 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 6 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 2117 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 2117 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 2117 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 221739 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 221739 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 221739 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 2071 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 2071 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 2071 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 221695 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 221695 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 221695 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 830917000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 830917000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 830917000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 824417000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 824417000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 824417000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.001139 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.001139 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.001139 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3747.274949 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3747.274949 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3747.274949 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3718.699114 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3718.699114 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3718.699114 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2527207 # number of replacements -system.cpu.dcache.tagsinuse 4087.569371 # Cycle average of tags in use -system.cpu.dcache.total_refs 440821768 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2531303 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 174.148163 # Average number of references to valid blocks. +system.cpu.dcache.replacements 2527930 # number of replacements +system.cpu.dcache.tagsinuse 4087.566272 # Cycle average of tags in use +system.cpu.dcache.total_refs 440586260 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2532026 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 174.005425 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 2135798000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4087.569371 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997942 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 292074612 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 147577545 # number of WriteReq hits -system.cpu.dcache.demand_hits 439652157 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 439652157 # number of overall hits -system.cpu.dcache.ReadReq_misses 3115587 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1582656 # number of WriteReq misses -system.cpu.dcache.demand_misses 4698243 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 4698243 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 51949082000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 37383634500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 89332716500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 89332716500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 295190199 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 4087.566272 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997941 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 291836002 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 147579227 # number of WriteReq hits +system.cpu.dcache.demand_hits 439415229 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 439415229 # number of overall hits +system.cpu.dcache.ReadReq_misses 3119681 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1580974 # number of WriteReq misses +system.cpu.dcache.demand_misses 4700655 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 4700655 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 52079313500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 37355392500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 89434706000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 89434706000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 294955683 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 444350400 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 444350400 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.010555 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.010610 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.010573 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.010573 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16673.930787 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 23620.821265 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 19014.068983 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 19014.068983 # average overall miss latency +system.cpu.dcache.demand_accesses 444115884 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 444115884 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.010577 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.010599 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.010584 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.010584 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16693.794494 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 23628.087812 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 19026.009354 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 19026.009354 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 74500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18625 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 2229206 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1355757 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 609338 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1965095 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1965095 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1759830 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 973318 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2733148 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2733148 # number of overall MSHR misses +system.cpu.dcache.writebacks 2229595 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1359154 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 607660 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1966814 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1966814 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1760527 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 973314 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2733841 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2733841 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14896925000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 17174770000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 32071695000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 32071695000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 14908482500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 17169522000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 32078004500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 32078004500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005962 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005969 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.006525 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.006151 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.006151 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8464.979572 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17645.589622 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 11734.342597 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 11734.342597 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.006156 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.006156 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8468.193047 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17640.270252 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11733.675989 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11733.675989 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 574699 # number of replacements -system.cpu.l2cache.tagsinuse 21595.701500 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3193363 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 593876 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.377154 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 271431195000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7794.557657 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13801.143843 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.237871 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.421177 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1432788 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 2229212 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 1238 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 524381 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1957169 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1957169 # number of overall hits -system.cpu.l2cache.ReadReq_misses 338369 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 208965 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 247135 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 585504 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 585504 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 11556474000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 9921000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 8477435500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 20033909500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 20033909500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1771157 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 2229212 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 210203 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 771516 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2542673 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2542673 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.191044 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.994110 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.320324 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.230271 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.230271 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34153.465595 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 47.476850 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34302.852692 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34216.520297 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34216.520297 # average overall miss latency +system.cpu.l2cache.replacements 574945 # number of replacements +system.cpu.l2cache.tagsinuse 21597.257673 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3194359 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 594122 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.376604 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 271429089000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7797.131828 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13800.125845 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.237950 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.421146 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1433279 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 2229601 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 1240 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 524400 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 1957679 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1957679 # number of overall hits +system.cpu.l2cache.ReadReq_misses 338611 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 208876 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 247152 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 585763 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 585763 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 11564612500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 9756500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 8478074500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 20042687000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 20042687000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1771890 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 2229601 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 210116 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 771552 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2543442 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2543442 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.191102 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.994098 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.320331 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.230303 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.230303 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34153.091601 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 46.709531 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34303.078672 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34216.375906 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34216.375906 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,31 +447,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 411193 # number of writebacks +system.cpu.l2cache.writebacks 411265 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 338369 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 208965 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 247135 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 585504 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 585504 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 338611 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 208876 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 247152 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 585763 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 585763 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10496162500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6478082000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7666148000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 18162310500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 18162310500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 10503665500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6475353000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7666739500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18170405000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18170405000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191044 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994110 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320324 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.230271 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.230271 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.870319 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.799177 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31020.082141 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31019.959727 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31019.959727 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191102 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994098 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320331 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.230303 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.230303 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.859071 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.943143 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31020.341733 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31020.062722 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31020.062722 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini index fdc891c59..da3b012b0 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -61,14 +62,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout index 190029619..d3e847fa3 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:30:34 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt index 3cf669902..c9073b3b2 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3416660 # Simulator instruction rate (inst/s) -host_mem_usage 206360 # Number of bytes of host memory used -host_seconds 447.51 # Real time elapsed on the host -host_tick_rate 1978121798 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1528988757 # Number of instructions simulated sim_seconds 0.885229 # Number of seconds simulated sim_ticks 885229360000 # Number of ticks simulated -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1063398 # Simulator instruction rate (inst/s) +host_tick_rate 615669149 # Simulator tick rate (ticks/s) +host_mem_usage 237896 # Number of bytes of host memory used +host_seconds 1437.83 # Real time elapsed on the host +sim_insts 1528988757 # Number of instructions simulated +system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 1770458721 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 1770458721 # Number of busy cycles -system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.num_insts 1528988757 # Number of instructions executed system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls system.cpu.num_int_insts 1528317615 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written -system.cpu.num_load_insts 384102160 # Number of load instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 533262345 # number of memory refs +system.cpu.num_load_insts 384102160 # Number of load instructions system.cpu.num_store_insts 149160185 # Number of store instructions -system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 1770458721 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini index 330cf56d3..e63456bf2 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -164,14 +165,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/20.parser/ref/x86/linux/simple-timing/simerr index 94d399eab..ac4ad20a5 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simerr +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index b7abf2775..268de88f4 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -1,14 +1,12 @@ -M5 Simulator System +Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:27:05 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing +gem5 compiled Jan 9 2012 14:18:02 +gem5 started Jan 9 2012 14:29:08 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index 9224e99d3..a96327ae0 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,223 +1,223 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2070048 # Simulator instruction rate (inst/s) -host_mem_usage 214112 # Number of bytes of host memory used -host_seconds 738.62 # Real time elapsed on the host -host_tick_rate 2245699490 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1528988757 # Number of instructions simulated sim_seconds 1.658730 # Number of seconds simulated sim_ticks 1658729604000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 384102189 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 22005.441660 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19005.440502 # average ReadReq mshr miss latency +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 746220 # Simulator instruction rate (inst/s) +host_tick_rate 809539282 # Simulator tick rate (ticks/s) +host_mem_usage 246668 # Number of bytes of host memory used +host_seconds 2048.98 # Real time elapsed on the host +sim_insts 1528988757 # Number of instructions simulated +system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.numCycles 3317459208 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 1528988757 # Number of instructions executed +system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls +system.cpu.num_int_insts 1528317615 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read +system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 533262345 # number of memory refs +system.cpu.num_load_insts 384102160 # Number of load instructions +system.cpu.num_store_insts 149160185 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 3317459208 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 1253 # number of replacements +system.cpu.icache.tagsinuse 882.231489 # Cycle average of tags in use +system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 882.231489 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.430777 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1068344296 # number of ReadReq hits +system.cpu.icache.demand_hits 1068344296 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1068344296 # number of overall hits +system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses +system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses +system.cpu.icache.overall_misses 2814 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 136878000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 136878000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 136878000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1068347110 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1068347110 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 48641.791045 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 48641.791045 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 48641.791045 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 2814 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 2814 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 128436000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 128436000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 128436000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 45641.791045 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 2514362 # number of replacements +system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use +system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4086.472055 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997674 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 382374775 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 38012508000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1727414 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 32830264000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1727414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27169.175798 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24169.168845 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 148369157 # number of WriteReq hits +system.cpu.dcache.demand_hits 530743932 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 530743932 # number of overall hits +system.cpu.dcache.ReadReq_misses 1727414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 791044 # number of WriteReq misses +system.cpu.dcache.demand_misses 2518458 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2518458 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 38012508000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 21492013500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 59504521500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 59504521500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 384102189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 533262390 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 533262390 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.005303 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 791044 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 19118876000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005303 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 791044 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.004723 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.004723 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 22005.441660 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 27169.175798 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 23627.363053 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 23627.363053 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 533262390 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 23627.363053 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency -system.cpu.dcache.demand_hits 530743932 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 59504521500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.004723 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2518458 # number of demand (read+write) misses +system.cpu.dcache.writebacks 2223170 # number of writebacks system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1727414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 791044 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2518458 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2518458 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 32830264000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 19118876000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 51949140000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 51949140000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005303 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.004723 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2518458 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4086.472055 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997674 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 533262390 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 23627.363053 # average overall miss latency +system.cpu.dcache.overall_mshr_miss_rate 0.004723 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19005.440502 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24169.168845 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 530743932 # number of overall hits -system.cpu.dcache.overall_miss_latency 59504521500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.004723 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2518458 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 51949140000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2518458 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2514362 # number of replacements -system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use -system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2223170 # number of writebacks -system.cpu.icache.ReadReq_accesses 1068347110 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 48641.791045 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 45641.791045 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1068344296 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 136878000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 128436000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1068347110 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 48641.791045 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency -system.cpu.icache.demand_hits 1068344296 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 136878000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses -system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 128436000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 2814 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 882.231489 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.430777 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 48641.791045 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1068344296 # number of overall hits -system.cpu.icache.overall_miss_latency 136878000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.overall_misses 2814 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 128436000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 2814 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1253 # number of replacements -system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 882.231489 # Cycle average of tags in use -system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.024190 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 568906 # number of replacements +system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3146531 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7549.128601 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13679.064710 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.230381 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.417452 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1398652 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 2223170 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 543011 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 12897722000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.313551 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_hits 1941663 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1941663 # number of overall hits +system.cpu.l2cache.ReadReq_misses 331576 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 248033 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9921320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313551 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 248033 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1730228 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1398652 # number of ReadReq hits +system.cpu.l2cache.demand_misses 579609 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 579609 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 17241952000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.191637 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 331576 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13263040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191637 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 331576 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_miss_latency 12897722000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 30139674000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 30139674000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1730228 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 2223170 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2223170 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2521272 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.191637 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.313551 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.229888 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.229888 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.024190 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000.010352 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000.010352 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2521272 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000.010352 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1941663 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 30139674000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.229888 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 579609 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 411709 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 331576 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 248033 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 579609 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 579609 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 13263040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 9921320000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 23184360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 23184360000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191637 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313551 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.229888 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 579609 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 7549.128601 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13679.064710 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.230381 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.417452 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000.010352 # average overall miss latency +system.cpu.l2cache.overall_mshr_miss_rate 0.229888 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1941663 # number of overall hits -system.cpu.l2cache.overall_miss_latency 30139674000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.229888 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 579609 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 23184360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.229888 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 579609 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 568906 # number of replacements -system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks. +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3146531 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 411709 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3317459208 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 3317459208 # Number of busy cycles -system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 1528988757 # Number of instructions executed -system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses -system.cpu.num_int_insts 1528317615 # number of integer instructions -system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read -system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written -system.cpu.num_load_insts 384102160 # Number of load instructions -system.cpu.num_mem_refs 533262345 # number of memory refs -system.cpu.num_store_insts 149160185 # Number of store instructions -system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |