diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2010-05-03 00:45:01 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-05-03 00:45:01 -0700 |
| commit | 8b0c83008e6c1964c9606a47213f11599ab186c5 (patch) | |
| tree | b15e4205be5850c21bcfa241b548173cb8a088b7 /tests/long/20.parser/ref/x86 | |
| parent | 2ee7a892092086db1bdf707438a9c10bf1426a69 (diff) | |
| download | gem5-8b0c83008e6c1964c9606a47213f11599ab186c5.tar.xz | |
X86: Update stats for the updated auxilliary vectors.
Diffstat (limited to 'tests/long/20.parser/ref/x86')
6 files changed, 132 insertions, 132 deletions
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini index e58df7993..5b5021cae 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -57,9 +57,9 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/parser +executable=/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout index 1c2b2b54d..f1c113f48 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:41:05 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:53:46 -M5 executing on SC2B0619 +M5 compiled May 2 2010 23:23:01 +M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch +M5 started May 2 2010 23:23:02 +M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -74,4 +74,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 868585211000 because target called exit() +Exiting @ tick 868585242000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt index e3dcb1667..6bb6e0dd2 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1408369 # Simulator instruction rate (inst/s) -host_mem_usage 192628 # Number of bytes of host memory used -host_seconds 1062.01 # Real time elapsed on the host -host_tick_rate 817869724 # Simulator tick rate (ticks/s) +host_inst_rate 3246924 # Simulator instruction rate (inst/s) +host_mem_usage 221228 # Number of bytes of host memory used +host_seconds 460.65 # Real time elapsed on the host +host_tick_rate 1885557129 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1495700470 # Number of instructions simulated +sim_insts 1495700521 # Number of instructions simulated sim_seconds 0.868585 # Number of seconds simulated -sim_ticks 868585211000 # Number of ticks simulated +sim_ticks 868585242000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1737170423 # number of cpu cycles simulated -system.cpu.num_insts 1495700470 # Number of instructions executed -system.cpu.num_refs 533262337 # Number of memory references +system.cpu.numCycles 1737170485 # number of cpu cycles simulated +system.cpu.num_insts 1495700521 # Number of instructions executed +system.cpu.num_refs 533262345 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini index c8eb88a42..aed4ce8e7 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini @@ -157,9 +157,9 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/parser +executable=/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index 458afbc15..02d865426 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:41:05 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:54:07 -M5 executing on SC2B0619 +M5 compiled May 2 2010 23:23:01 +M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch +M5 started May 2 2010 23:23:02 +M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -74,4 +74,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 1722331568000 because target called exit() +Exiting @ tick 1722332515000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index 87bf15b21..a0f899d5b 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,82 +1,82 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 925832 # Simulator instruction rate (inst/s) -host_mem_usage 200280 # Number of bytes of host memory used -host_seconds 1615.52 # Real time elapsed on the host -host_tick_rate 1066115675 # Simulator tick rate (ticks/s) +host_inst_rate 1698687 # Simulator instruction rate (inst/s) +host_mem_usage 228888 # Number of bytes of host memory used +host_seconds 880.50 # Real time elapsed on the host +host_tick_rate 1956075066 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1495700470 # Number of instructions simulated -sim_seconds 1.722332 # Number of seconds simulated -sim_ticks 1722331568000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 384102182 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 24153.691272 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21153.690114 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 382374810 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 41722410000 # number of ReadReq miss cycles +sim_insts 1495700521 # Number of instructions simulated +sim_seconds 1.722333 # Number of seconds simulated +sim_ticks 1722332515000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 384102189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 24152.982435 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21152.981277 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 382374775 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 41722200000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1727372 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 36540292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 1727414 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 36539956000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1727372 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 149160200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.912307 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.912307 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 147694869 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 82058407500 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_mshr_misses 1727414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.911625 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.911625 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 147694849 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 82059582500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.009824 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1465331 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 77662414500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 1465352 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 77663526500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.009824 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1465331 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1465352 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 210.745406 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 533262382 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 38769.912986 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35769.912360 # average overall mshr miss latency -system.cpu.dcache.demand_hits 530069679 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 123780817500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 533262390 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 38769.450220 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35769.449593 # average overall mshr miss latency +system.cpu.dcache.demand_hits 530069624 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 123781782500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.005987 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3192703 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 3192766 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 114202706500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 114203482500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.005987 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 3192703 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 3192766 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997757 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4086.814341 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 533262382 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 38769.912986 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35769.912360 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.997759 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4086.820737 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 533262390 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 38769.450220 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35769.449593 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 530069679 # number of overall hits -system.cpu.dcache.overall_miss_latency 123780817500 # number of overall miss cycles +system.cpu.dcache.overall_hits 530069624 # number of overall hits +system.cpu.dcache.overall_miss_latency 123781782500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.005987 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3192703 # number of overall misses +system.cpu.dcache.overall_misses 3192766 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 114202706500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 114203482500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.005987 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 3192703 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 3192766 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2514317 # number of replacements -system.cpu.dcache.sampled_refs 2518413 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2514362 # number of replacements +system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4086.814341 # Cycle average of tags in use -system.cpu.dcache.total_refs 530743969 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8217895000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 1463113 # number of writebacks -system.cpu.icache.ReadReq_accesses 1068347073 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tagsinuse 4086.820737 # Cycle average of tags in use +system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8218050000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 1463134 # number of writebacks +system.cpu.icache.ReadReq_accesses 1068347110 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 48626.865672 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 45626.865672 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1068344259 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1068344296 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 136836000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses @@ -85,16 +85,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # ms system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 379653.254797 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1068347073 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1068347110 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 48626.865672 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 45626.865672 # average overall mshr miss latency -system.cpu.icache.demand_hits 1068344259 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1068344296 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 136836000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses @@ -106,12 +106,12 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.occ_%::0 0.433368 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 887.538461 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1068347073 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 887.538061 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 48626.865672 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 45626.865672 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1068344259 # number of overall hits +system.cpu.icache.overall_hits 1068344296 # number of overall hits system.cpu.icache.overall_miss_latency 136836000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses system.cpu.icache.overall_misses 2814 # number of overall misses @@ -124,92 +124,92 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 1253 # number of replacements system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 887.538461 # Cycle average of tags in use -system.cpu.icache.total_refs 1068344259 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 887.538061 # Cycle average of tags in use +system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 791041 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014538 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 41134143500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 41134299500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 791041 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 31641640000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 791044 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 31641760000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 791041 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1730186 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 791044 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1730228 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1310266 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 21835840000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.242702 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 419920 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 16796800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242702 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 419920 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 674290 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.203458 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_hits 1310327 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 21834852000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.242685 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 419901 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 16796040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242685 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 419901 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 674308 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.126631 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 35055800000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 35056684000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 674290 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26971600000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 674308 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26972320000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 674290 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 1463113 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 1463113 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 674308 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 1463134 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1463134 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.423900 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.424249 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2521227 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 2521272 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000.009497 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1310266 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 62969983500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.480306 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1210961 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 1310327 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 62969151500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.480291 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1210945 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 48438440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.480306 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1210961 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 48437800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.480291 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1210945 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.111890 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.413414 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 3666.426168 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13546.751396 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 2521227 # number of overall (read+write) accesses +system.cpu.l2cache.occ_%::0 0.111884 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.413412 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 3666.207378 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13546.690457 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000.009497 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1310266 # number of overall hits -system.cpu.l2cache.overall_miss_latency 62969983500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.480306 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1210961 # number of overall misses +system.cpu.l2cache.overall_hits 1310327 # number of overall hits +system.cpu.l2cache.overall_miss_latency 62969151500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.480291 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1210945 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 48438440000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.480306 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1210961 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 48437800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.480291 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1210945 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 664073 # number of replacements -system.cpu.l2cache.sampled_refs 680479 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 664035 # number of replacements +system.cpu.l2cache.sampled_refs 680440 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17213.177564 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2329892 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 921652677000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 481653 # number of writebacks +system.cpu.l2cache.tagsinuse 17212.897835 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2329996 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 921653687000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 481618 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3444663136 # number of cpu cycles simulated -system.cpu.num_insts 1495700470 # Number of instructions executed -system.cpu.num_refs 533262337 # Number of memory references +system.cpu.numCycles 3444665030 # number of cpu cycles simulated +system.cpu.num_insts 1495700521 # Number of instructions executed +system.cpu.num_refs 533262345 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- |