tests: update statistics for change caused by vsyscall support in x86

Caused by a slight change in memory layout.

3 files changed, 115 insertions, 118 deletions

diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
index 5f5b1b01c..a7ed66f8a 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -45,7 +45,6 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -80,7 +79,6 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -115,7 +113,6 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
index a5dbe2b41..a11db4e1e 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug  8 2009 12:09:45
-M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch
-M5 started Aug  8 2009 12:09:46
-M5 executing on tater
+M5 compiled Nov  8 2009 16:16:58
+M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff
+M5 started Nov  8 2009 16:39:28
+M5 executing on maize
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -74,4 +74,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 1722352562000 because target called exit()
+Exiting @ tick 1722331568000 because target called exit()
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
index c62dd0754..0e665b6ef 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -1,84 +1,84 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 924480                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 209588                       # Number of bytes of host memory used
-host_seconds                                  1617.88                       # Real time elapsed on the host
-host_tick_rate                             1064572030                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1459378                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 198104                       # Number of bytes of host memory used
+host_seconds                                  1024.89                       # Real time elapsed on the host
+host_tick_rate                             1680505604                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1495700470                       # Number of instructions simulated
-sim_seconds                                  1.722353                       # Number of seconds simulated
-sim_ticks                                1722352562000                       # Number of ticks simulated
+sim_seconds                                  1.722332                       # Number of seconds simulated
+sim_ticks                                1722331568000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          384102182                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              382375369                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    41698498000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.004496                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              1726813                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  36518057000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.004496                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         1726813                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_avg_miss_latency 24153.691272                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21153.690114                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              382374810                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    41722410000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.004497                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses              1727372                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  36540292000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.004497                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses         1727372                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses         149160200                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.912355                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.912355                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             147694052                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   82104159500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.009829                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             1466148                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency  77705715500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.009829                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses        1466148                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 55999.912307                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.912307                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             147694869                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   82058407500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.009824                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             1465331                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency  77662414500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.009824                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses        1465331                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 210.782575                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                 210.745406                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           533262382                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 38773.620317                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35773.619690                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               530069421                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency    123802657500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.005988                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               3192961                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 38769.912986                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35769.912360                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               530069679                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency    123780817500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.005987                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               3192703                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 114223772500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.005988                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          3192961                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 114202706500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.005987                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          3192703                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses          533262382                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 38773.620317                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35773.619690                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 38769.912986                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35769.912360                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              530069421                       # number of overall hits
-system.cpu.dcache.overall_miss_latency   123802657500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.005988                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              3192961                       # number of overall misses
+system.cpu.dcache.overall_hits              530069679                       # number of overall hits
+system.cpu.dcache.overall_miss_latency   123780817500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.005987                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              3192703                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 114223772500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.005988                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         3192961                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 114202706500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.005987                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         3192703                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                2513875                       # number of replacements
-system.cpu.dcache.sampled_refs                2517971                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                2514317                       # number of replacements
+system.cpu.dcache.sampled_refs                2518413                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4086.831173                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                530744411                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             8217762000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  1463913                       # number of writebacks
+system.cpu.dcache.tagsinuse               4086.814341                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                530743969                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             8217895000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                  1463113                       # number of writebacks
 system.cpu.icache.ReadReq_accesses         1068347073                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 48417.910448                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 45417.910448                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 48626.865672                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 45626.865672                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits             1068344259                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      136248000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency      136836000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000003                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                 2814                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency    127806000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    128394000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000003                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses            2814                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
@@ -90,29 +90,29 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses          1068347073                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 48417.910448                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 45417.910448                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 48626.865672                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 45626.865672                       # average overall mshr miss latency
 system.cpu.icache.demand_hits              1068344259                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       136248000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency       136836000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000003                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                  2814                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    127806000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    128394000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000003                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses             2814                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses         1068347073                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 48417.910448                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 45417.910448                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 48626.865672                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 45626.865672                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits             1068344259                       # number of overall hits
-system.cpu.icache.overall_miss_latency      136248000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency      136836000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000003                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                 2814                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    127806000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    128394000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000003                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses            2814                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -120,86 +120,86 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                   1253                       # number of replacements
 system.cpu.icache.sampled_refs                   2814                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                887.487990                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                887.538461                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1068344259                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses          791158                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014536                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_accesses          791041                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014538                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency  41140227500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency  41134143500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            791158                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency  31646320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_misses            791041                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency  31641640000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       791158                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses           1729627                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_mshr_misses       791041                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses           1730186                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits               1310104                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   21815196000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.242551                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses              419523                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  16780920000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.242551                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses         419523                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses         674990                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.214655                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadReq_hits               1310266                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency   21835840000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.242702                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses              419920                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  16796800000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.242702                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses         419920                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses         674290                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.203458                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency  35092200000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency  35055800000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses           674990                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency  26999600000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses           674290                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency  26971600000                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses       674990                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses         1463913                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits             1463913                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses       674290                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses         1463113                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits             1463113                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  3.428066                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  3.423900                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            2520785                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000.009499                       # average overall miss latency
+system.cpu.l2cache.demand_accesses            2521227                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000.009497                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                1310104                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    62955423500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.480279                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              1210681                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                1310266                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency    62969983500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.480306                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses              1210961                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency  48427240000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.480279                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         1210681                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency  48438440000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.480306                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses         1210961                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses           2520785                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000.009499                       # average overall miss latency
+system.cpu.l2cache.overall_accesses           2521227                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000.009497                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits               1310104                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   62955423500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.480279                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             1210681                       # number of overall misses
+system.cpu.l2cache.overall_hits               1310266                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency   62969983500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.480306                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses             1210961                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency  48427240000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.480279                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        1210681                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency  48438440000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.480306                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses        1210961                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                663513                       # number of replacements
-system.cpu.l2cache.sampled_refs                679921                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                664073                       # number of replacements
+system.cpu.l2cache.sampled_refs                680479                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             17216.037197                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 2330814                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          921771494000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                  481430                       # number of writebacks
+system.cpu.l2cache.tagsinuse             17213.177564                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 2329892                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          921652677000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                  481653                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       3444705124                       # number of cpu cycles simulated
+system.cpu.numCycles                       3444663136                       # number of cpu cycles simulated
 system.cpu.num_insts                       1495700470                       # Number of instructions executed
 system.cpu.num_refs                         533262337                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             551                       # Number of system calls