diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-13 17:44:32 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-13 17:44:32 -0800 |
| commit | b046f3feb6e54f128e8868fcb807d0d5ac0d7ba7 (patch) | |
| tree | 7b91be055f2b91c0707ca431adf22dc157bfa7f4 /tests/long/20.parser/ref | |
| parent | 4e1adf85f77edf761466af3568576d3f9134a14c (diff) | |
| download | gem5-b046f3feb6e54f128e8868fcb807d0d5ac0d7ba7.tar.xz | |
X86: Update stats for the reduced register reads.
Diffstat (limited to 'tests/long/20.parser/ref')
7 files changed, 395 insertions, 395 deletions
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini index 8363ae747..da344ea4b 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini @@ -488,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout index 4d3b5f29b..50a40bebc 100755 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 10 2011 20:38:27 +M5 revision 944f6c89dbb7 7941 default qtip regwidthdecstats.patch tip +M5 started Feb 10 2011 20:38:30 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -26,10 +26,10 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success +info: Increasing stack size by one page. * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor info: Increasing stack size by one page. -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -74,4 +74,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 817002039000 because target called exit() +Exiting @ tick 698491025500 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt index c39e8dfae..76386c514 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 160923 # Simulator instruction rate (inst/s) -host_mem_usage 240360 # Number of bytes of host memory used -host_seconds 9501.35 # Real time elapsed on the host -host_tick_rate 85987979 # Simulator tick rate (ticks/s) +host_inst_rate 136830 # Simulator instruction rate (inst/s) +host_mem_usage 244640 # Number of bytes of host memory used +host_seconds 11174.38 # Real time elapsed on the host +host_tick_rate 62508267 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1528988756 # Number of instructions simulated -sim_seconds 0.817002 # Number of seconds simulated -sim_ticks 817002039000 # Number of ticks simulated +sim_seconds 0.698491 # Number of seconds simulated +sim_ticks 698491025500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 197674461 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 215147546 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 172887264 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 187312240 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 17901021 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 215739151 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 215739151 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 17887438 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 187888188 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 187888188 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 149758588 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 8186576 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 10029766 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1552269342 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.985002 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.301395 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1350871673 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.131853 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.433209 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 694185983 44.72% 44.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 509617235 32.83% 77.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 176087126 11.34% 88.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 105147186 6.77% 95.67% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 31137095 2.01% 97.67% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 11224991 0.72% 98.40% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 11192282 0.72% 99.12% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 5490868 0.35% 99.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 8186576 0.53% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 568349245 42.07% 42.07% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 413717350 30.63% 72.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 172321570 12.76% 85.46% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 110104358 8.15% 93.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 43035291 3.19% 96.79% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 18507275 1.37% 98.16% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 8248201 0.61% 98.77% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 6558617 0.49% 99.26% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 10029766 0.74% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1552269342 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1350871673 # Number of insts commited each cycle system.cpu.commit.COM:count 1528988756 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,432 +44,432 @@ system.cpu.commit.COM:loads 384102160 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 533262345 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 17902344 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 17888761 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 459109010 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 257046446 # The number of squashed insts skipped by commit system.cpu.committedInsts 1528988756 # Number of Instructions Simulated system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated -system.cpu.cpi 1.068683 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.068683 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 352008034 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14100.976079 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8499.435037 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 350035037 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 27821183500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.005605 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1972997 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 237485 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 14750871500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.004930 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1735512 # number of ReadReq MSHR misses +system.cpu.cpi 0.913664 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.913664 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 334229227 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14263.584813 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8537.168964 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 332171764 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 29346798000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.006156 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 2057463 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 319131 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 14840434000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005201 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1738332 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 15942.157352 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12645.445755 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 148213244 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 15096537500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.006349 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 946957 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 159966 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 9951852000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 16290.992476 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12654.921756 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 148197195 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 15688323500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.006456 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 963006 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 176041 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 9958980500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005276 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 786991 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 786965 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 197.709284 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 190.400689 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 501168235 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 14698.081203 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9792.941178 # average overall mshr miss latency -system.cpu.dcache.demand_hits 498248281 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 42917721000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005826 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2919954 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 397451 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 24702723500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005033 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2522503 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 483389428 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 14909.976398 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9820.395185 # average overall mshr miss latency +system.cpu.dcache.demand_hits 480368959 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 45035121500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.006249 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3020469 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 495172 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 24799414500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005224 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2525297 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997749 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4086.780222 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 501168235 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 14698.081203 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9792.941178 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.997741 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4086.747665 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 483389428 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 14909.976398 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9820.395185 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 498248281 # number of overall hits -system.cpu.dcache.overall_miss_latency 42917721000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005826 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2919954 # number of overall misses -system.cpu.dcache.overall_mshr_hits 397451 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 24702723500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005033 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2522503 # number of overall MSHR misses +system.cpu.dcache.overall_hits 480368959 # number of overall hits +system.cpu.dcache.overall_miss_latency 45035121500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.006249 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3020469 # number of overall misses +system.cpu.dcache.overall_mshr_hits 495172 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 24799414500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005224 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2525297 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2516044 # number of replacements -system.cpu.dcache.sampled_refs 2520140 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2518885 # number of replacements +system.cpu.dcache.sampled_refs 2522981 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4086.780222 # Cycle average of tags in use -system.cpu.dcache.total_refs 498255076 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3876881000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2224034 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 25470243 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 2119227193 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 403203369 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 1116867689 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 71636028 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 6728041 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 215739151 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 165973622 # Number of cache lines fetched -system.cpu.fetch.Cycles 1190006834 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 2725815 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1144873460 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 1839 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 29822694 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.132031 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 165973622 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 197674461 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.700655 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1623905370 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.336094 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.273592 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4086.747665 # Cycle average of tags in use +system.cpu.dcache.total_refs 480377321 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3312879000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2225275 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 18280435 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 1869219380 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 343093281 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 984893533 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 39316255 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 4604424 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 187888188 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 144979108 # Number of cache lines fetched +system.cpu.fetch.Cycles 1039380252 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2070461 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 999560833 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 1828 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 17988626 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.134496 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 144979108 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 172887264 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.715514 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1390187928 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.363495 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.275570 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 477535637 29.41% 29.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 564706157 34.77% 64.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 259330057 15.97% 80.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 261180842 16.08% 96.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 22809127 1.40% 97.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 31399021 1.93% 99.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 502829 0.03% 99.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12 0.00% 99.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6441688 0.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 388271402 27.93% 27.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 493387093 35.49% 63.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 229970387 16.54% 79.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224046516 16.12% 96.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21915192 1.58% 97.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25802023 1.86% 99.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 493192 0.04% 99.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12 0.00% 99.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6302111 0.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1623905370 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 10 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 165973622 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 22741.617211 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 19372.661290 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 165966882 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 153278500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000041 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 6740 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 540 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 120110500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000037 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 6200 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 1390187928 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 9 # number of floating regfile reads +system.cpu.icache.ReadReq_accesses 144979108 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 22807.726664 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 19441.756997 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 144972391 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 153199500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 6717 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 536 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120169500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000043 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 6181 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 49795.025203 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 43679.520036 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 165973622 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 22741.617211 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 19372.661290 # average overall mshr miss latency -system.cpu.icache.demand_hits 165966882 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 153278500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000041 # miss rate for demand accesses -system.cpu.icache.demand_misses 6740 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 540 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 120110500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000037 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 6200 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 144979108 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 22807.726664 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 19441.756997 # average overall mshr miss latency +system.cpu.icache.demand_hits 144972391 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 153199500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses +system.cpu.icache.demand_misses 6717 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 536 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120169500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000043 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 6181 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.436573 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 894.100654 # Average occupied blocks per context -system.cpu.icache.overall_accesses 165973622 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 22741.617211 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 19372.661290 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.450710 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 923.054085 # Average occupied blocks per context +system.cpu.icache.overall_accesses 144979108 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 22807.726664 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 19441.756997 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 165966882 # number of overall hits -system.cpu.icache.overall_miss_latency 153278500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000041 # miss rate for overall accesses -system.cpu.icache.overall_misses 6740 # number of overall misses -system.cpu.icache.overall_mshr_hits 540 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 120110500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 6200 # number of overall MSHR misses +system.cpu.icache.overall_hits 144972391 # number of overall hits +system.cpu.icache.overall_miss_latency 153199500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses +system.cpu.icache.overall_misses 6717 # number of overall misses +system.cpu.icache.overall_mshr_hits 536 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120169500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000043 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 6181 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1750 # number of replacements -system.cpu.icache.sampled_refs 3333 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1737 # number of replacements +system.cpu.icache.sampled_refs 3319 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 894.100654 # Cycle average of tags in use -system.cpu.icache.total_refs 165966819 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 923.054085 # Cycle average of tags in use +system.cpu.icache.total_refs 144972327 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 10098709 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 158001976 # Number of branches executed +system.cpu.idleCycles 6794124 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 154306305 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.044762 # Inst execution rate -system.cpu.iew.EXEC:refs 586795750 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 160862585 # Number of stores executed +system.cpu.iew.EXEC:rate 1.173655 # Inst execution rate +system.cpu.iew.EXEC:refs 571924541 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 156120222 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2114014731 # num instructions consuming a value -system.cpu.iew.WB:count 1694146367 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.583880 # average fanout of values written-back +system.cpu.iew.WB:consumers 1636048139 # num instructions consuming a value +system.cpu.iew.WB:count 1628444279 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.722963 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1234331323 # num instructions producing a value -system.cpu.iew.WB:rate 1.036807 # insts written-back per cycle -system.cpu.iew.WB:sent 1697627373 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 18573506 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 6103126 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 508224738 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 579 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 12080656 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 194089353 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 1988097398 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 425933165 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 26013466 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1707144682 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 381189 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1182802327 # num instructions producing a value +system.cpu.iew.WB:rate 1.165687 # insts written-back per cycle +system.cpu.iew.WB:sent 1630313962 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 18753816 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4588629 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 454402470 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 570 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 11948307 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 170547501 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1786034876 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 415804319 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21119599 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1639574511 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 357621 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 10588 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 71636028 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 847228 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 9695 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 39316255 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 668139 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 72909425 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 277837 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 80610216 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 294173 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 11954619 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 832 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 124122578 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 44929168 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 11954619 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 280770 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 18292736 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 3876226209 # number of integer regfile reads -system.cpu.int_regfile_writes 1582892637 # number of integer regfile writes -system.cpu.ipc 0.935731 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.935731 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1927969 0.11% 0.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1131725915 65.30% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 435582288 25.13% 90.54% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 163921976 9.46% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 154646 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 837 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 70300310 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 21387316 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 154646 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 515713 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 18238103 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 3040879637 # number of integer regfile reads +system.cpu.int_regfile_writes 1524435086 # number of integer regfile writes +system.cpu.ipc 1.094494 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.094494 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1929805 0.12% 0.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1078730229 64.96% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 421270517 25.37% 90.44% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 158763559 9.56% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1733158148 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1029171 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000594 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 1660694110 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 783660 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.000472 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 182 0.02% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 466697 45.35% 45.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 562292 54.64% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 37602 4.80% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 575954 73.50% 78.29% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 170104 21.71% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1623905370 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.067278 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.066518 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1390187928 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.194582 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.080366 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 608633589 37.48% 37.48% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 503635145 31.01% 68.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 353739534 21.78% 90.28% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 117719188 7.25% 97.53% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 32883027 2.02% 99.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 6737765 0.41% 99.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 234496 0.01% 99.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 322546 0.02% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 80 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 424313305 30.52% 30.52% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 484307598 34.84% 65.36% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 321495427 23.13% 88.49% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 117467117 8.45% 96.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 33024815 2.38% 99.31% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 8635258 0.62% 99.93% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 892156 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 52195 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 57 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1623905370 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.060682 # Inst issue rate -system.cpu.iq.fp_alu_accesses 24 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 48 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses +system.cpu.iq.ISSUE:issued_per_cycle::total 1390187928 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.188773 # Inst issue rate +system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 9 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 1732259326 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 5091250901 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 1694146357 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 2453039449 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 1988096819 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1733158148 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 579 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 452995728 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1010995901 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 789062 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34275.179377 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.682665 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 541538 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 8483929500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.313694 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 247524 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7673660500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313694 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 247524 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1734408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34153.383782 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31001.108327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1401925 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 11355419500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.191698 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 332483 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10307341500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191698 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 332483 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 2863 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 24.346581 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31002.148228 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_hits 70 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_miss_latency 68000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 0.975550 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 2793 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 86589000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.975550 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 2793 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2224034 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2224034 # number of Writeback hits +system.cpu.iq.int_alu_accesses 1659547943 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 4712390399 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1628444270 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 2036676469 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1786034306 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1660694110 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 570 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 250539717 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 30635 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 457117092 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 789066 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34257.778038 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.587520 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 541510 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 8480718500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.313733 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 247556 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7674629000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313733 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 247556 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1737232 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34158.153227 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.616867 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1403818 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 11388806500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.191923 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 333414 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 10336706500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191923 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 333414 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 2858 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 24.740050 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.358551 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_hits 69 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_miss_latency 69000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 0.975857 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 2789 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 86460000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.975857 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 2789 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2225275 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2225275 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.356881 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 5.353417 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2523470 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34205.361315 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31001.353432 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1943463 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 19839349000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.229845 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 580007 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 2526298 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34200.604162 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31002.178254 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1945328 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 19869525000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.229969 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 580970 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 17981002000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.229845 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 580007 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 18011335500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.229969 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 580970 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.233067 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.421257 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 7637.149597 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13803.753842 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 2523470 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34205.361315 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31001.353432 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.234251 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.418210 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 7675.941579 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13703.908999 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 2526298 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34200.604162 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31002.178254 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1943463 # number of overall hits -system.cpu.l2cache.overall_miss_latency 19839349000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.229845 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 580007 # number of overall misses +system.cpu.l2cache.overall_hits 1945328 # number of overall hits +system.cpu.l2cache.overall_miss_latency 19869525000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.229969 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 580970 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 17981002000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.229845 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 580007 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 18011335500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.229969 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 580970 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 569254 # number of replacements -system.cpu.l2cache.sampled_refs 588327 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 570217 # number of replacements +system.cpu.l2cache.sampled_refs 589293 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 21440.903439 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3151598 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 469235659000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 411363 # number of writebacks -system.cpu.memDep0.conflictingLoads 151128770 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 47539398 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 508224738 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194089353 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 947795380 # number of misc regfile reads -system.cpu.numCycles 1634004079 # number of cpu cycles simulated +system.cpu.l2cache.tagsinuse 21379.850577 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3154731 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 377230361000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 411577 # number of writebacks +system.cpu.memDep0.conflictingLoads 169465698 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 40622935 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 454402470 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 170547499 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 909615360 # number of misc regfile reads +system.cpu.numCycles 1396982052 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 11181498 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 7556367 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 8162354 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 430755417 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1988994 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 37 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 6064799926 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2072679155 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1965930252 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1095363349 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 71636028 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 14962968 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 538631225 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:IQFullEvents 5884693 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 361176398 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2156935 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 61 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 4527342452 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 1840516856 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1743217369 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 971079353 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 39316255 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 11053475 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 315918342 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 168 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 6064799758 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 6110 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 566 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 21122292 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 563 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 3532180532 # The number of ROB reads -system.cpu.rob.rob_writes 4048956705 # The number of ROB writes -system.cpu.timesIdled 351337 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:int_rename_lookups 4527342284 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 6080 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 557 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 18505861 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 554 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3126877109 # The number of ROB reads +system.cpu.rob.rob_writes 3611419620 # The number of ROB writes +system.cpu.timesIdled 237370 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout index 70ab31a10..ac3a396e6 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:12 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:52 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt index 836ed1519..8c759990e 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 904614 # Simulator instruction rate (inst/s) -host_mem_usage 227300 # Number of bytes of host memory used -host_seconds 1690.21 # Real time elapsed on the host -host_tick_rate 523739013 # Simulator tick rate (ticks/s) +host_inst_rate 2138348 # Simulator instruction rate (inst/s) +host_mem_usage 227776 # Number of bytes of host memory used +host_seconds 715.03 # Real time elapsed on the host +host_tick_rate 1238025751 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1528988757 # Number of instructions simulated sim_seconds 0.885229 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 1528988757 # Number of instructions executed system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses system.cpu.num_int_insts 1528317615 # number of integer instructions -system.cpu.num_int_register_reads 4418676175 # number of times the integer registers were read +system.cpu.num_int_register_reads 3724500872 # number of times the integer registers were read system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written system.cpu.num_load_insts 384102160 # Number of load instructions system.cpu.num_mem_refs 533262345 # number of memory refs diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index 9e491e500..881a57025 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:36:47 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:52 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index 2cd323573..ea3a6a172 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 738382 # Simulator instruction rate (inst/s) -host_mem_usage 235020 # Number of bytes of host memory used -host_seconds 2070.73 # Real time elapsed on the host -host_tick_rate 801036637 # Simulator tick rate (ticks/s) +host_inst_rate 1467057 # Simulator instruction rate (inst/s) +host_mem_usage 235504 # Number of bytes of host memory used +host_seconds 1042.22 # Real time elapsed on the host +host_tick_rate 1591542347 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1528988757 # Number of instructions simulated sim_seconds 1.658730 # Number of seconds simulated @@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 1528988757 # Number of instructions executed system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses system.cpu.num_int_insts 1528317615 # number of integer instructions -system.cpu.num_int_register_reads 4418676175 # number of times the integer registers were read +system.cpu.num_int_register_reads 3724500872 # number of times the integer registers were read system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written system.cpu.num_load_insts 384102160 # Number of load instructions system.cpu.num_mem_refs 533262345 # number of memory refs |