diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-07-10 12:56:09 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-07-10 12:56:09 -0500 |
| commit | 3ebfe2eb0124b0524952c59f04580a55eb36edff (patch) | |
| tree | 3d48c5d7bddaa51413b4504b7bc17635e67e14a7 /tests/long/20.parser/ref | |
| parent | 3396fd9e84358346b60437a7635c9cc5f331017f (diff) | |
| download | gem5-3ebfe2eb0124b0524952c59f04580a55eb36edff.tar.xz | |
O3: Update stats for fetch and bp changes.
Diffstat (limited to 'tests/long/20.parser/ref')
7 files changed, 812 insertions, 813 deletions
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini index 91e8c0469..da98ab03d 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,14 +494,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/20.parser/ref/arm/linux/o3-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/simerr +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout index 5a0807465..9edf46eb3 100755 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout @@ -1,16 +1,10 @@ -Redirecting stdout to build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing/simerr -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 16 2011 15:11:25 -M5 started May 16 2011 15:29:17 -M5 executing on nadc-0271 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:43 +gem5 started Jul 9 2011 01:33:51 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -73,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 320953109000 because target called exit() +Exiting @ tick 302517583000 because target called exit() diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt index b11250106..954793f3d 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.320953 # Number of seconds simulated -sim_ticks 320953109000 # Number of ticks simulated +sim_seconds 0.302518 # Number of seconds simulated +sim_ticks 302517583000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40042 # Simulator instruction rate (inst/s) -host_tick_rate 22415184 # Simulator tick rate (ticks/s) -host_mem_usage 260460 # Number of bytes of host memory used -host_seconds 14318.56 # Real time elapsed on the host -sim_insts 573342262 # Number of instructions simulated +host_inst_rate 48998 # Simulator instruction rate (inst/s) +host_tick_rate 25853029 # Simulator tick rate (ticks/s) +host_mem_usage 270368 # Number of bytes of host memory used +host_seconds 11701.44 # Real time elapsed on the host +sim_insts 573342442 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,297 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 641906219 # number of cpu cycles simulated +system.cpu.numCycles 605035167 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 223949599 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 179054613 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 19156129 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 184229626 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 147971030 # Number of BTB hits +system.cpu.BPredUnit.lookups 237948628 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 189643896 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18525471 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 200558633 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 165003293 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 11972868 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2532941 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 130565917 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 973113322 # Number of instructions fetch has processed -system.cpu.fetch.Branches 223949599 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 159943898 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 241546376 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 21862580 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2406 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 130565917 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3998860 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 637850640 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.791502 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.743865 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 12776963 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2655849 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 165318082 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1053599180 # Number of instructions fetch has processed +system.cpu.fetch.Branches 237948628 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 177780256 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 271034430 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 85133152 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 100456864 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 3051 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 121417 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 151931838 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4658920 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 600617430 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.083903 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.829133 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 396316059 62.13% 62.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20357816 3.19% 65.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 35705192 5.60% 70.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 35959525 5.64% 76.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 37219035 5.84% 82.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 17602838 2.76% 85.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 18536216 2.91% 88.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 14275483 2.24% 90.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61878476 9.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 329595233 54.88% 54.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24765043 4.12% 59.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43080599 7.17% 66.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 41413060 6.90% 73.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43530596 7.25% 80.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 16033141 2.67% 82.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 19523127 3.25% 86.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 16376620 2.73% 88.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 66300011 11.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 637850640 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.348882 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.515974 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 274650627 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 79437827 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 227463937 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2944119 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 53354130 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 31952595 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76091 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1091620209 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 217331 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 53354130 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 289506174 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9893108 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49317817 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 215240896 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20538515 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1036732054 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 236 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6072390 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 9974912 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 19 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1156982067 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4582431546 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4582430193 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1353 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672201056 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 484781006 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2811540 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2811485 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 54423240 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 192516932 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 113728531 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 52019514 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 56045106 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 898220409 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4649392 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 742085900 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4028217 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 325034737 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 902951971 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 771526 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 637850640 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.163416 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.451606 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 600617430 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.393281 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.741385 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 185610198 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 93209648 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 249465251 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8754516 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 63577817 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 34830541 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 109065 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1190327461 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 219958 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 63577817 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 203483134 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12711979 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52382429 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 240021493 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 28440578 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1124560978 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 631 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 9752153 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 15058133 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1694 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1243412483 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4977837521 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4977834393 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3128 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672201344 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 571211134 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2776537 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2776073 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 72944066 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 210041655 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 130199534 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 69466757 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 73938650 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 989222584 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4552609 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 764881922 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1674381 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 418150078 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1236634953 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 674707 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 600617430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.273493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.529486 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 296239264 46.44% 46.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 133409185 20.92% 67.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 102098632 16.01% 83.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53722534 8.42% 91.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 32322089 5.07% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 11168911 1.75% 98.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5441714 0.85% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2057834 0.32% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1390477 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 269133638 44.81% 44.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 116546536 19.40% 64.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 93441125 15.56% 79.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 61796479 10.29% 90.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 37339082 6.22% 96.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12656566 2.11% 98.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5425017 0.90% 99.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3357457 0.56% 99.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 921530 0.15% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 637850640 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 600617430 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 95830 1.04% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5443662 59.10% 60.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3670689 39.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 286700 3.30% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5674602 65.33% 68.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2725077 31.37% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 503818075 67.89% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 366199 0.05% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 82 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 163695097 22.06% 90.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 74206444 10.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 522376749 68.30% 68.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 381409 0.05% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 80 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 170546214 22.30% 90.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 71577467 9.36% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 742085900 # Type of FU issued -system.cpu.iq.rate 1.156066 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9210181 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012411 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2135260638 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1228450518 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 694522935 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 200 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 304 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 764881922 # Type of FU issued +system.cpu.iq.rate 1.264194 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8686379 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011356 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2140741838 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1412472990 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 713443043 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 196 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 472 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 751295979 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 102 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5771553 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 773568201 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 100 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 6159543 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 65743781 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 15629 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 596063 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 56124460 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 83268468 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 32978 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 628275 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 72595427 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 24980 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 144 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 27007 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 156 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 53354130 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2618576 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 142825 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 912051296 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 21556193 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 192516932 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 113728531 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2788498 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 84227 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8711 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 596063 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 17931306 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6522754 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 24454060 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 711877956 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 154430876 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30207944 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 63577817 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2968769 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 160563 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1003649799 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 12343350 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 210041655 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 130199534 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2755333 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 81778 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 10213 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 628275 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 18784960 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6284429 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25069389 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 737887948 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 162551175 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 26993974 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9181495 # number of nop insts executed -system.cpu.iew.exec_refs 222561224 # number of memory reference insts executed -system.cpu.iew.exec_branches 143781551 # Number of branches executed -system.cpu.iew.exec_stores 68130348 # Number of stores executed -system.cpu.iew.exec_rate 1.109006 # Inst execution rate -system.cpu.iew.wb_sent 704134955 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 694522951 # cumulative count of insts written-back -system.cpu.iew.wb_producers 388125156 # num instructions producing a value -system.cpu.iew.wb_consumers 688020690 # num instructions consuming a value +system.cpu.iew.exec_nop 9874606 # number of nop insts executed +system.cpu.iew.exec_refs 230127290 # number of memory reference insts executed +system.cpu.iew.exec_branches 150192140 # Number of branches executed +system.cpu.iew.exec_stores 67576115 # Number of stores executed +system.cpu.iew.exec_rate 1.219579 # Inst execution rate +system.cpu.iew.wb_sent 726019609 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 713443059 # cumulative count of insts written-back +system.cpu.iew.wb_producers 405782893 # num instructions producing a value +system.cpu.iew.wb_consumers 732949927 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.081970 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.564118 # average fanout of values written-back +system.cpu.iew.wb_rate 1.179176 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.553630 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 574686146 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 337368429 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3877866 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 21251956 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 584496511 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.983216 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.594536 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 574686326 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 428980158 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3877902 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 20816789 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 537039614 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.070100 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.725106 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 311654164 53.32% 53.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 150316632 25.72% 79.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 55227209 9.45% 88.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 24753339 4.23% 92.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 15848741 2.71% 95.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 6546524 1.12% 96.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7691194 1.32% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2289333 0.39% 98.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10169375 1.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 281877385 52.49% 52.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 136335503 25.39% 77.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 48132590 8.96% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 21242728 3.96% 90.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19119215 3.56% 94.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6739612 1.25% 95.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8597333 1.60% 97.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3363443 0.63% 97.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11631805 2.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 584496511 # Number of insts commited each cycle -system.cpu.commit.count 574686146 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 537039614 # Number of insts commited each cycle +system.cpu.commit.count 574686326 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184377221 # Number of memory references committed -system.cpu.commit.loads 126773150 # Number of loads committed +system.cpu.commit.refs 184377293 # Number of memory references committed +system.cpu.commit.loads 126773186 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 120192335 # Number of branches committed +system.cpu.commit.branches 120192371 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473702077 # Number of committed integer instructions. +system.cpu.commit.int_insts 473702221 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 10169375 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 11631805 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1486374573 # The number of ROB reads -system.cpu.rob.rob_writes 1877592139 # The number of ROB writes -system.cpu.timesIdled 93100 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4055579 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 573342262 # Number of Instructions Simulated -system.cpu.committedInsts_total 573342262 # Number of Instructions Simulated -system.cpu.cpi 1.119586 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.119586 # CPI: Total CPI of All Threads -system.cpu.ipc 0.893187 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.893187 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3288876394 # number of integer regfile reads -system.cpu.int_regfile_writes 807633235 # number of integer regfile writes +system.cpu.rob.rob_reads 1529067155 # The number of ROB reads +system.cpu.rob.rob_writes 2071246317 # The number of ROB writes +system.cpu.timesIdled 105999 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4417737 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 573342442 # Number of Instructions Simulated +system.cpu.committedInsts_total 573342442 # Number of Instructions Simulated +system.cpu.cpi 1.055277 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.055277 # CPI: Total CPI of All Threads +system.cpu.ipc 0.947618 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.947618 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3393544591 # number of integer regfile reads +system.cpu.int_regfile_writes 828738212 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1209708694 # number of misc regfile reads -system.cpu.misc_regfile_writes 4464272 # number of misc regfile writes -system.cpu.icache.replacements 11767 # number of replacements -system.cpu.icache.tagsinuse 1053.166926 # Cycle average of tags in use -system.cpu.icache.total_refs 130550979 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 13545 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 9638.315172 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 1294615924 # number of misc regfile reads +system.cpu.misc_regfile_writes 4464344 # number of misc regfile writes +system.cpu.icache.replacements 14868 # number of replacements +system.cpu.icache.tagsinuse 1047.725210 # Cycle average of tags in use +system.cpu.icache.total_refs 151911457 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16514 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 9198.949800 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1053.166926 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.514242 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 130550990 # number of ReadReq hits -system.cpu.icache.demand_hits 130550990 # number of demand (read+write) hits -system.cpu.icache.overall_hits 130550990 # number of overall hits -system.cpu.icache.ReadReq_misses 14927 # number of ReadReq misses -system.cpu.icache.demand_misses 14927 # number of demand (read+write) misses -system.cpu.icache.overall_misses 14927 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 215353500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 215353500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 215353500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 130565917 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 130565917 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 130565917 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000114 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000114 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000114 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 14427.111945 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 14427.111945 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 14427.111945 # average overall miss latency +system.cpu.icache.occ_blocks::0 1047.725210 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.511585 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 151911844 # number of ReadReq hits +system.cpu.icache.demand_hits 151911844 # number of demand (read+write) hits +system.cpu.icache.overall_hits 151911844 # number of overall hits +system.cpu.icache.ReadReq_misses 19994 # number of ReadReq misses +system.cpu.icache.demand_misses 19994 # number of demand (read+write) misses +system.cpu.icache.overall_misses 19994 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 277167000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 277167000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 277167000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 151931838 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 151931838 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 151931838 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000132 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000132 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000132 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 13862.508753 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 13862.508753 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 13862.508753 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,146 +352,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 2 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1072 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1072 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1072 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 13855 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 13855 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 13855 # number of overall MSHR misses +system.cpu.icache.writebacks 29 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 1670 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1670 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1670 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 18324 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 18324 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 18324 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 147833000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 147833000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 147833000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 184845500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 184845500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 184845500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000106 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000106 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000106 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 10670.010826 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 10670.010826 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 10670.010826 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000121 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000121 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000121 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 10087.617332 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 10087.617332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 10087.617332 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1189612 # number of replacements -system.cpu.dcache.tagsinuse 4060.806862 # Cycle average of tags in use -system.cpu.dcache.total_refs 200134121 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1193708 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.657518 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 6159317000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4060.806862 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.991408 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 142442366 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 52854608 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 2604415 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 2232135 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 195296974 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 195296974 # number of overall hits -system.cpu.dcache.ReadReq_misses 1102250 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1384698 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 36 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 2486948 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2486948 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11846428500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 20406027500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 313000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 32252456000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 32252456000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 143544616 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1208536 # number of replacements +system.cpu.dcache.tagsinuse 4059.803539 # Cycle average of tags in use +system.cpu.dcache.total_refs 207709608 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1212632 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 171.288246 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5997963000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4059.803539 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.991163 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 150052810 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 52876507 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 2544785 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 2232171 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 202929317 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 202929317 # number of overall hits +system.cpu.dcache.ReadReq_misses 1147618 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1362799 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 51 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 2510417 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2510417 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 12147896500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 20751705500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 582000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 32899602000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 32899602000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 151200428 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 2604451 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 2232135 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 197783922 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 197783922 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.007679 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.025529 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000014 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.012574 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.012574 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 10747.496938 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 14736.807232 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 8694.444444 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 12968.689333 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 12968.689333 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 2544836 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 2232171 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 205439734 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 205439734 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.007590 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.025126 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000020 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.012220 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.012220 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 10585.313667 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 15227.267924 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 11411.764706 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 13105.233911 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 13105.233911 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 172500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 98500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 32 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 20 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5390.625000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4925 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1065401 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 244002 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1048961 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 36 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1292963 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1292963 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 858248 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 335737 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1193985 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1193985 # number of overall MSHR misses +system.cpu.dcache.writebacks 1079332 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 271534 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1024501 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 51 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1296035 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1296035 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 876084 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 338298 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1214382 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1214382 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 6157877500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4228090500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 10385968000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 10385968000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 6267336500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4269582000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10536918500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10536918500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005979 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006190 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.006037 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.006037 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7174.939528 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12593.460060 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8698.574940 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8698.574940 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005794 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.005911 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.005911 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7153.807740 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12620.772219 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8676.774277 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8676.774277 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 214616 # number of replacements -system.cpu.l2cache.tagsinuse 21258.843371 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1538764 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 234845 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.552254 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 231195370000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7817.837138 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13441.006233 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.238581 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.410187 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 742273 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1065403 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 160 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 231247 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 973520 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 973520 # number of overall hits -system.cpu.l2cache.ReadReq_misses 129152 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 104568 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 233720 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 233720 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 4416243000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 547000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3581590000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 7997833000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 7997833000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 871425 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1065403 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 272 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 335815 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1207240 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1207240 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.148208 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.411765 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.311386 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.193599 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.193599 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34194.151078 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4883.928571 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34251.300589 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34219.720178 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34219.720178 # average overall miss latency +system.cpu.l2cache.replacements 217502 # number of replacements +system.cpu.l2cache.tagsinuse 21268.774974 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1567233 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 237739 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.592242 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7619.579259 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13649.195715 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.232531 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.416540 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 761070 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1079361 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 1189 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 231140 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 992210 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 992210 # number of overall hits +system.cpu.l2cache.ReadReq_misses 130897 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 521 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 105763 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 236660 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 236660 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 4476495000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 5061500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3624223500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 8100718500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 8100718500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 891967 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1079361 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 1710 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 336903 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 1228870 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 1228870 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.146751 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.304678 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.313927 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.192583 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.192583 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34198.606538 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 9714.971209 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34267.404480 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34229.352235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34229.352235 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -498,32 +500,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 169760 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 15 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 129137 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 104568 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 233705 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 233705 # number of overall MSHR misses +system.cpu.l2cache.writebacks 170191 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 22 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 130875 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 521 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 105763 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 236638 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 236638 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4006675000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3473000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3242222500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 7248897500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 7248897500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4061689500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 16157000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3279601500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 7341291000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 7341291000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.148191 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.411765 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.311386 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.193586 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.193586 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31026.545452 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31008.928571 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.876559 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31017.297448 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31017.297448 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146726 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.304678 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313927 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.192566 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.192566 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.876791 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31011.516315 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31008.968165 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31023.297188 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31023.297188 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini index 523530b80..5d31afbd4 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,14 +494,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout index c4825a4e7..d1c3d672a 100755 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 27 2011 02:06:34 -gem5 started Jun 27 2011 02:06:35 -gem5 executing on burrito -command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:15 +gem5 started Jul 8 2011 20:37:07 +gem5 executing on u200439-lin.austin.arm.com +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -21,6 +21,7 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success +info: Increasing stack size by one page. * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor info: Increasing stack size by one page. @@ -32,7 +33,6 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -77,4 +77,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 584042944000 because target called exit() +Exiting @ tick 589091030500 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt index a6db3838d..0a390d5cd 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,249 +1,252 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.584043 # Number of seconds simulated -sim_ticks 584042944000 # Number of ticks simulated +sim_seconds 0.589091 # Number of seconds simulated +sim_ticks 589091030500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 221280 # Simulator instruction rate (inst/s) -host_tick_rate 84524523 # Simulator tick rate (ticks/s) -host_mem_usage 274300 # Number of bytes of host memory used -host_seconds 6909.75 # Real time elapsed on the host +host_inst_rate 58676 # Simulator instruction rate (inst/s) +host_tick_rate 22606879 # Simulator tick rate (ticks/s) +host_mem_usage 302632 # Number of bytes of host memory used +host_seconds 26058.04 # Real time elapsed on the host sim_insts 1528988756 # Number of instructions simulated system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 1168085889 # number of cpu cycles simulated +system.cpu.numCycles 1178182062 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 253398223 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 253398223 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16660589 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 238496117 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 219579135 # Number of BTB hits +system.cpu.BPredUnit.lookups 273761240 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 273761240 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16674451 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 263536261 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 242767527 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 188493207 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1362528555 # Number of instructions fetch has processed -system.cpu.fetch.Branches 253398223 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 219579135 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 442066407 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 19282041 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 77357 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 188493207 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3791136 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1143941897 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.224075 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.207990 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 225401733 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1479491232 # Number of instructions fetch has processed +system.cpu.fetch.Branches 273761240 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 242767527 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 481293494 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 151906633 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 310358472 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 81567 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 542630 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 210837280 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3978525 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1150020801 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.401549 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.263992 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 706029092 61.72% 61.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32745689 2.86% 64.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38225778 3.34% 67.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34592742 3.02% 70.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20873132 1.82% 72.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 39592075 3.46% 76.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 44500061 3.89% 80.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 36282476 3.17% 83.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 191100852 16.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 673309594 58.55% 58.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 35910144 3.12% 61.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 42110719 3.66% 65.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 37429485 3.25% 68.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 23065552 2.01% 70.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 42484626 3.69% 74.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 50557962 4.40% 78.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39843815 3.46% 82.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 205308904 17.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1143941897 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.216935 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.166463 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 421359771 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 186435003 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 405946069 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21628019 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 108573035 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2494021022 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 108573035 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 460289272 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50662445 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15855 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 387005567 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 137395723 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2428811074 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8205 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 53921903 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 70830357 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2267152647 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5703018907 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5703000611 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 18296 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1150020801 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.232359 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.255741 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 295424105 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 258223017 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 403450338 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 60580436 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 132342905 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2687346589 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 53 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 132342905 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 338937810 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 65386701 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28780 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 418304086 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 195020519 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2631430094 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 26828 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 78975062 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 100019003 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2450674662 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6174029113 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6173774259 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 254854 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 839853620 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2555 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2515 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 298765601 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 586920489 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 222789217 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 352764399 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 138805015 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2327145816 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 9782 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1903699652 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 745209 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 795395556 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1355118976 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 9229 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1143941897 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.664158 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.649963 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1023375635 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3023 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3014 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 414859898 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 629524584 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 242192886 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 419436220 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 160455315 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2509631726 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 14401 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1981481069 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1143998 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 979086329 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1684803071 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13848 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1150020801 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.722996 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.682483 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 364171044 31.83% 31.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 265972258 23.25% 55.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 191418370 16.73% 71.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 151056709 13.20% 85.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 94863070 8.29% 93.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 46725885 4.08% 97.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 20369113 1.78% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 8499440 0.74% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 866008 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 371533820 32.31% 32.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 234816386 20.42% 52.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 195375199 16.99% 69.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 160336940 13.94% 83.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104083103 9.05% 92.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 52438845 4.56% 97.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24322326 2.11% 99.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6470584 0.56% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 643598 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1143941897 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1150020801 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1290505 11.43% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7282962 64.50% 75.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2717631 24.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2000225 14.58% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9217501 67.18% 81.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2502434 18.24% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2277009 0.12% 0.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1273302138 66.89% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 457949055 24.06% 91.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170171450 8.94% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2582215 0.13% 0.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1339393426 67.60% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 465725544 23.50% 91.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173779884 8.77% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1903699652 # Type of FU issued -system.cpu.iq.rate 1.629760 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11291098 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005931 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4963377358 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3125135181 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1859937909 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 150 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 7364 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 35 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1912713667 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 74 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 121955986 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1981481069 # Type of FU issued +system.cpu.iq.rate 1.681812 # Inst issue rate +system.cpu.iq.fu_busy_cnt 13720160 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006924 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5127845391 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3491473273 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1932208550 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1706 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 91974 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 40 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1992618257 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 757 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 130432763 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 202818329 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 145118 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 2595412 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 73631154 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 245422424 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 85551 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 2844514 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 93035934 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1267 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 2121 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 108573035 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9607775 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1579187 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2327155598 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2263253 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 586920489 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 222791339 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 9782 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1056355 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 44992 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 2595412 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15396927 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2702189 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18099116 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1873386406 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 447925301 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30313246 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 132342905 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11594389 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3099842 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2509646127 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 554822 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 629524584 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 242196119 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14401 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2636094 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 28755 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 2844514 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15750968 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2390539 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18141507 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1946393180 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 456989279 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 35087889 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 613922207 # number of memory reference insts executed -system.cpu.iew.exec_branches 173516320 # Number of branches executed -system.cpu.iew.exec_stores 165996906 # Number of stores executed -system.cpu.iew.exec_rate 1.603809 # Inst execution rate -system.cpu.iew.wb_sent 1866315288 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1859937944 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1434930162 # num instructions producing a value -system.cpu.iew.wb_consumers 2113232937 # num instructions consuming a value +system.cpu.iew.exec_refs 625199049 # number of memory reference insts executed +system.cpu.iew.exec_branches 178040376 # Number of branches executed +system.cpu.iew.exec_stores 168209770 # Number of stores executed +system.cpu.iew.exec_rate 1.652031 # Inst execution rate +system.cpu.iew.wb_sent 1940174748 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1932208590 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1494691214 # num instructions producing a value +system.cpu.iew.wb_consumers 2239401377 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.592296 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.679021 # average fanout of values written-back +system.cpu.iew.wb_rate 1.639992 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.667451 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 798170363 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 980665483 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16691926 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1035368862 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.476758 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.996244 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16734282 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1017677896 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.502429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.032638 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 433054636 41.83% 41.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 271974415 26.27% 68.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 102879563 9.94% 78.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 102354239 9.89% 87.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 37870792 3.66% 91.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24412946 2.36% 93.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10660961 1.03% 94.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10611646 1.02% 95.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 41549664 4.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 426781992 41.94% 41.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 262838337 25.83% 67.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 100636861 9.89% 77.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 98086664 9.64% 87.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 37562129 3.69% 90.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27349053 2.69% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 11151176 1.10% 94.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9457604 0.93% 95.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 43814080 4.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1035368862 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1017677896 # Number of insts commited each cycle system.cpu.commit.count 1528988756 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 533262345 # Number of memory references committed @@ -253,48 +256,48 @@ system.cpu.commit.branches 149758588 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 41549664 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 43814080 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3320978317 # The number of ROB reads -system.cpu.rob.rob_writes 4762953278 # The number of ROB writes -system.cpu.timesIdled 612203 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24143992 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3483518055 # The number of ROB reads +system.cpu.rob.rob_writes 5151797430 # The number of ROB writes +system.cpu.timesIdled 664618 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28161261 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1528988756 # Number of Instructions Simulated system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated -system.cpu.cpi 0.763960 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.763960 # CPI: Total CPI of All Threads -system.cpu.ipc 1.308969 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.308969 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3113988878 # number of integer regfile reads -system.cpu.int_regfile_writes 1735338379 # number of integer regfile writes -system.cpu.fp_regfile_reads 35 # number of floating regfile reads -system.cpu.misc_regfile_reads 1026178630 # number of misc regfile reads -system.cpu.icache.replacements 9690 # number of replacements -system.cpu.icache.tagsinuse 963.166837 # Cycle average of tags in use -system.cpu.icache.total_refs 188230465 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11136 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 16902.879400 # Average number of references to valid blocks. +system.cpu.cpi 0.770563 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.770563 # CPI: Total CPI of All Threads +system.cpu.ipc 1.297753 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.297753 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3171957706 # number of integer regfile reads +system.cpu.int_regfile_writes 1803005697 # number of integer regfile writes +system.cpu.fp_regfile_reads 40 # number of floating regfile reads +system.cpu.misc_regfile_reads 1059979955 # number of misc regfile reads +system.cpu.icache.replacements 11725 # number of replacements +system.cpu.icache.tagsinuse 992.230576 # Cycle average of tags in use +system.cpu.icache.total_refs 210562203 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 13217 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 15931.164636 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 963.166837 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.470296 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 188237743 # number of ReadReq hits -system.cpu.icache.demand_hits 188237743 # number of demand (read+write) hits -system.cpu.icache.overall_hits 188237743 # number of overall hits -system.cpu.icache.ReadReq_misses 255464 # number of ReadReq misses -system.cpu.icache.demand_misses 255464 # number of demand (read+write) misses -system.cpu.icache.overall_misses 255464 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 1671443500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 1671443500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 1671443500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 188493207 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 188493207 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 188493207 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.001355 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.001355 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.001355 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 6542.775107 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 6542.775107 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 6542.775107 # average overall miss latency +system.cpu.icache.occ_blocks::0 992.230576 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.484488 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 210569051 # number of ReadReq hits +system.cpu.icache.demand_hits 210569051 # number of demand (read+write) hits +system.cpu.icache.overall_hits 210569051 # number of overall hits +system.cpu.icache.ReadReq_misses 268229 # number of ReadReq misses +system.cpu.icache.demand_misses 268229 # number of demand (read+write) misses +system.cpu.icache.overall_misses 268229 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 1801320500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 1801320500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 1801320500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 210837280 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 210837280 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 210837280 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.001272 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.001272 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.001272 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 6715.606814 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 6715.606814 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 6715.606814 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -303,60 +306,60 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 7 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1428 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1428 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1428 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 254036 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 254036 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 254036 # number of overall MSHR misses +system.cpu.icache.writebacks 8 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 1476 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1476 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1476 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 266753 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 266753 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 266753 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 873542000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 873542000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 873542000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 963323500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 963323500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 963323500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.001348 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.001348 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.001348 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3438.654364 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3438.654364 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3438.654364 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.001265 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.001265 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.001265 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3611.293969 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3611.293969 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3611.293969 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2526737 # number of replacements -system.cpu.dcache.tagsinuse 4088.695382 # Cycle average of tags in use -system.cpu.dcache.total_refs 470726270 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2530833 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 185.996575 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 2167120000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4088.695382 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.998217 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 321866059 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 147543837 # number of WriteReq hits -system.cpu.dcache.demand_hits 469409896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 469409896 # number of overall hits -system.cpu.dcache.ReadReq_misses 3006715 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1616364 # number of WriteReq misses -system.cpu.dcache.demand_misses 4623079 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 4623079 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 47957140000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 38289086000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 86246226000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 86246226000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 324872774 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2529482 # number of replacements +system.cpu.dcache.tagsinuse 4088.837997 # Cycle average of tags in use +system.cpu.dcache.total_refs 471282230 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533578 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 186.014494 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 2156497000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4088.837997 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.998251 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 322424417 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 147507556 # number of WriteReq hits +system.cpu.dcache.demand_hits 469931973 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 469931973 # number of overall hits +system.cpu.dcache.ReadReq_misses 3022528 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1652645 # number of WriteReq misses +system.cpu.dcache.demand_misses 4675173 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 4675173 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 48854800500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 39692092500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 88546893000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 88546893000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 325446945 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 474032975 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 474032975 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.009255 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.010836 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.009753 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.009753 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 15950.011890 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 23688.405582 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 18655.581270 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 18655.581270 # average overall miss latency +system.cpu.dcache.demand_accesses 474607146 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 474607146 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.009287 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.011080 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.009851 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.009851 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16163.555970 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 24017.313156 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 18939.810997 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 18939.810997 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -365,75 +368,75 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 2229867 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1247117 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 605322 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1852439 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1852439 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1759598 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1011042 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2770640 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2770640 # number of overall MSHR misses +system.cpu.dcache.writebacks 2230911 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1260687 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 634109 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1894796 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1894796 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1761841 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1018536 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2780377 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2780377 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14841801000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 18214921000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 33056722000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 33056722000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 14865117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 18574591000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 33439708000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 33439708000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005416 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006778 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.005845 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.005845 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8434.768055 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18015.988455 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 11931.078018 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 11931.078018 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005414 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006828 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.005858 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.005858 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8437.263635 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18236.558158 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12027.040937 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12027.040937 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 574893 # number of replacements -system.cpu.l2cache.tagsinuse 21475.591540 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3187531 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 594020 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.366033 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 306954721000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7759.826991 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13715.764549 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.236811 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.418572 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1427752 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 2229874 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 1226 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 528421 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1956173 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1956173 # number of overall hits -system.cpu.l2cache.ReadReq_misses 338145 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 241551 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 247520 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 585665 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 585665 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 11551149000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 10207000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 8480925000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 20032074000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 20032074000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1765897 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 2229874 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 242777 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 775941 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2541838 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2541838 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.191486 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.994950 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.318993 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.230410 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.230410 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34160.342457 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 42.256087 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34263.594861 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34203.980091 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34203.980091 # average overall miss latency +system.cpu.l2cache.replacements 576328 # number of replacements +system.cpu.l2cache.tagsinuse 21485.488039 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3192646 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 595469 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.361565 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 312361641000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7744.786330 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13740.701709 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.236352 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.419333 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1431746 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 2230919 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 1301 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 527734 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 1959480 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1959480 # number of overall hits +system.cpu.l2cache.ReadReq_misses 339175 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 252088 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 248002 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 587177 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 587177 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 11584401000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 11543000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 8495722000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 20080123000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 20080123000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1770921 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 2230919 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 253389 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 775736 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2546657 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2546657 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.191525 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.994866 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.319699 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.230568 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.230568 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34154.642883 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 45.789566 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34256.667285 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34197.734244 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34197.734244 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,32 +445,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 412030 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 338144 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 241551 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 247520 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 585664 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 585664 # number of overall MSHR misses +system.cpu.l2cache.writebacks 412300 # number of writebacks +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 339175 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 252088 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 248002 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 587177 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 587177 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10484231000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7489077000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7673754000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 18157985000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 18157985000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 10515780500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7815593500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7689085500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18204866000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18204866000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191486 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994950 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.318993 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.230410 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.230410 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.225584 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31004.123353 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31002.561409 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.099620 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.099620 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191525 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994866 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.319699 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.230568 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.230568 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31003.996462 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.433325 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31004.126983 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.051589 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.051589 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |