diff options
| author | Steve Reinhardt <stever@gmail.com> | 2010-09-09 14:40:19 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2010-09-09 14:40:19 -0400 |
| commit | 9e45ada1718b6df9310757fdc7cd78db4695516f (patch) | |
| tree | c5cc9f2173f36e38addd8ca08e32ac010e56ef73 /tests/long/20.parser | |
| parent | 12497284949cb5418e6bc403723c034aee655666 (diff) | |
| download | gem5-9e45ada1718b6df9310757fdc7cd78db4695516f.tar.xz | |
stats: update stats for preceding coherence changes
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
Diffstat (limited to 'tests/long/20.parser')
6 files changed, 218 insertions, 212 deletions
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini index 31d1c564f..003dd533c 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini @@ -152,7 +152,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing +cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/20.parser/ref/arm/linux/simple-timing/simout index ea21d5acf..73953840b 100755 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing/simout +Redirecting stderr to build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 24 2010 15:34:40 -M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase -M5 started Aug 24 2010 15:39:26 +M5 compiled Aug 26 2010 13:52:30 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:57:01 M5 executing on zizzer -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -72,4 +74,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 755274721000 because target called exit() +Exiting @ tick 745672616000 because target called exit() diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt index 7851b8b50..24713e5f3 100644 --- a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1894447 # Simulator instruction rate (inst/s) -host_mem_usage 213780 # Number of bytes of host memory used -host_seconds 295.32 # Real time elapsed on the host -host_tick_rate 2557466745 # Simulator tick rate (ticks/s) +host_inst_rate 1125820 # Simulator instruction rate (inst/s) +host_mem_usage 214880 # Number of bytes of host memory used +host_seconds 496.95 # Real time elapsed on the host +host_tick_rate 1500512692 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 559470527 # Number of instructions simulated -sim_seconds 0.755275 # Number of seconds simulated -sim_ticks 755274721000 # Number of ticks simulated +sim_seconds 0.745673 # Number of seconds simulated +sim_ticks 745672616000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 127326326 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 22055.619697 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19055.619697 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 20914.908888 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17914.908888 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 126543330 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 17269462000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 16376290000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.006150 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 782996 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14920474000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 14027302000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.006150 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 782996 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 55727847 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.902227 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.902227 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 54940305 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 44102275000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.014132 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 787542 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 41739649000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.014132 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 787542 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 53833.507889 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50833.507889 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 55072849 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 35260840000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.011754 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 654998 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 33295846000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.011754 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 654998 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 159.673059 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 183054173 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 39076.887665 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36076.887665 # average overall mshr miss latency -system.cpu.dcache.demand_hits 181483635 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 61371737000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.008580 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1570538 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 35909.141485 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 32909.141485 # average overall mshr miss latency +system.cpu.dcache.demand_hits 181616179 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 51637130000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.007856 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1437994 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 56660123000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.008580 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1570538 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 47323148000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.007856 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1437994 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.993060 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4067.574815 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.992972 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4067.215006 # Average occupied blocks per context system.cpu.dcache.overall_accesses 183054173 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 39076.887665 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36076.887665 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 35909.141485 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 32909.141485 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 181483635 # number of overall hits -system.cpu.dcache.overall_miss_latency 61371737000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.008580 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1570538 # number of overall misses +system.cpu.dcache.overall_hits 181616179 # number of overall hits +system.cpu.dcache.overall_miss_latency 51637130000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.007856 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1437994 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 56660123000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.008580 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1570538 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 47323148000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.007856 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1437994 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 1135200 # number of replacements system.cpu.dcache.sampled_refs 1139296 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4067.574815 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4067.215006 # Cycle average of tags in use system.cpu.dcache.total_refs 181914877 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 11579638000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 784411 # number of writebacks +system.cpu.dcache.warmup_cycle 11578483000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 808512 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -83,13 +83,13 @@ system.cpu.dtb.write_accesses 0 # DT system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.icache.ReadReq_accesses 512145761 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 24746.983769 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 21746.983769 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 512134240 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 285110000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 250547000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 250505000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -101,31 +101,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 512145761 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 24746.983769 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 21746.983769 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency system.cpu.icache.demand_hits 512134240 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 285110000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 250547000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 250505000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.485758 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 994.831789 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.485313 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 993.921198 # Average occupied blocks per context system.cpu.icache.overall_accesses 512145761 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 24746.983769 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 21746.983769 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 512134240 # number of overall hits -system.cpu.icache.overall_miss_latency 285110000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses system.cpu.icache.overall_misses 11521 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 250547000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 250505000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 9788 # number of replacements system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 994.831789 # Cycle average of tags in use +system.cpu.icache.tagsinuse 993.921198 # Cycle average of tags in use system.cpu.icache.total_refs 512134240 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -150,36 +150,37 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 356300 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 18527600000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 356300 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 14252000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 356300 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 33786 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 16770728000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.905175 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 322514 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 12900560000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.905175 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 322514 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 794517 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 641390 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 7962604000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.192730 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 153127 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 6125080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.192730 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 153127 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 431242 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51990.715190 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_hits 662657 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 6856720000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.165962 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 131860 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 5274400000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165962 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 131860 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 298698 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51993.732800 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 22420580000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 15530424000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 431242 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 17249680000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 298698 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11947920000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 431242 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 784411 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 784411 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 298698 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 808512 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 808512 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.037361 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.737661 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -188,44 +189,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 1150817 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 641390 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 26490204000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.442666 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 509427 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 696443 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 23627448000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.394827 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 454374 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 20377080000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.442666 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 509427 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 18174960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.394827 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 454374 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.106439 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.402713 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 3487.785932 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13196.100733 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.184240 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.380639 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 6037.178832 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 12472.788257 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 1150817 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 641390 # number of overall hits -system.cpu.l2cache.overall_miss_latency 26490204000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.442666 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 509427 # number of overall misses +system.cpu.l2cache.overall_hits 696443 # number of overall hits +system.cpu.l2cache.overall_miss_latency 23627448000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.394827 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 454374 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 20377080000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.442666 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 509427 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 18174960000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.394827 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 454374 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 258533 # number of replacements -system.cpu.l2cache.sampled_refs 276277 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 232496 # number of replacements +system.cpu.l2cache.sampled_refs 251560 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16683.886665 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1115430 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 531606891000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 206160 # number of writebacks +system.cpu.l2cache.tagsinuse 18509.967089 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1191806 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 525324932000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 186433 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1510549442 # number of cpu cycles simulated +system.cpu.numCycles 1491345232 # number of cpu cycles simulated system.cpu.num_insts 559470527 # Number of instructions executed system.cpu.num_refs 184987503 # Number of memory references system.cpu.workload.PROG:num_syscalls 548 # Number of system calls diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini index 7ded93665..675fb37c6 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini @@ -152,7 +152,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index 02d865426..fb5635e2e 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 2 2010 23:23:01 -M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch -M5 started May 2 2010 23:23:02 -M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing +M5 compiled Aug 26 2010 13:20:12 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:22:00 +M5 executing on zizzer +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -74,4 +76,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 1722332515000 because target called exit() +Exiting @ tick 1701783891000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index a0f899d5b..d803c2eef 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1698687 # Simulator instruction rate (inst/s) -host_mem_usage 228888 # Number of bytes of host memory used -host_seconds 880.50 # Real time elapsed on the host -host_tick_rate 1956075066 # Simulator tick rate (ticks/s) +host_inst_rate 1040513 # Simulator instruction rate (inst/s) +host_mem_usage 213908 # Number of bytes of host memory used +host_seconds 1437.46 # Real time elapsed on the host +host_tick_rate 1183878785 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1495700521 # Number of instructions simulated -sim_seconds 1.722333 # Number of seconds simulated -sim_ticks 1722332515000 # Number of ticks simulated +sim_seconds 1.701784 # Number of seconds simulated +sim_ticks 1701783891000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 384102189 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 24152.982435 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21152.981277 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 22845.361911 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19845.360753 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 382374775 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 41722200000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 39463398000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 1727414 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 36539956000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 34281154000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1727414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.911625 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.911625 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 147694849 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 82059582500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.009824 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1465352 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 77663526500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009824 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1465352 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 53546.298194 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50546.298194 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 147974496 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 63490113500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.007949 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1185705 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 59932998500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.007949 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1185705 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 533262390 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 38769.450220 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35769.449593 # average overall mshr miss latency -system.cpu.dcache.demand_hits 530069624 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 123781782500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005987 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3192766 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 35341.333979 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 32341.333293 # average overall mshr miss latency +system.cpu.dcache.demand_hits 530349271 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 102953511500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005463 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2913119 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 114203482500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005987 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 3192766 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 94214152500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005463 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2913119 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997759 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4086.820737 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.997733 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4086.713108 # Average occupied blocks per context system.cpu.dcache.overall_accesses 533262390 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 38769.450220 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35769.449593 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 35341.333979 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 32341.333293 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 530069624 # number of overall hits -system.cpu.dcache.overall_miss_latency 123781782500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005987 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3192766 # number of overall misses +system.cpu.dcache.overall_hits 530349271 # number of overall hits +system.cpu.dcache.overall_miss_latency 102953511500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005463 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2913119 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 114203482500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005987 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 3192766 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 94214152500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005463 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2913119 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 2514362 # number of replacements system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4086.820737 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4086.713108 # Cycle average of tags in use system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8218050000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 1463134 # number of writebacks +system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 1528950 # number of writebacks system.cpu.icache.ReadReq_accesses 1068347110 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 48626.865672 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 45626.865672 # average ReadReq mshr miss latency @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 2814 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.433368 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 887.538061 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.433486 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 887.780127 # Average occupied blocks per context system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 48626.865672 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 45626.865672 # average overall mshr miss latency @@ -124,90 +124,91 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 1253 # number of replacements system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 887.538061 # Cycle average of tags in use +system.cpu.icache.tagsinuse 887.780127 # Cycle average of tags in use system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014538 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.015933 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 41134299500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 791044 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 31641760000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 791044 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 69270 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 37532259500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.912432 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 721774 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 28870960000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.912432 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 721774 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 1730228 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1310327 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 21834852000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.242685 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 419901 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 16796040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242685 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 419901 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 674308 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.126631 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_hits 1364108 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 19038240000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.211602 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 366120 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 14644800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.211602 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 366120 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 394661 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51994.993171 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 35056684000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 20520396000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 674308 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26972320000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 394661 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 15786440000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 674308 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 1463134 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 1463134 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 394661 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 1528950 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1528950 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.424249 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.977137 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 2521272 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000.009497 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000.010571 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1310327 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 62969151500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.480291 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1210945 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 1433378 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 56570499500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.431486 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1087894 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 48437800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.480291 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1210945 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 43515760000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.431486 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1087894 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.111884 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.413412 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 3666.207378 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13546.690457 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.230883 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.374106 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 7565.560471 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 12258.710159 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000.009497 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000.010571 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1310327 # number of overall hits -system.cpu.l2cache.overall_miss_latency 62969151500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.480291 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1210945 # number of overall misses +system.cpu.l2cache.overall_hits 1433378 # number of overall hits +system.cpu.l2cache.overall_miss_latency 56570499500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.431486 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1087894 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 48437800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.480291 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1210945 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 43515760000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.431486 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1087894 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 664035 # number of replacements -system.cpu.l2cache.sampled_refs 680440 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 603454 # number of replacements +system.cpu.l2cache.sampled_refs 621473 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17212.897835 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2329996 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 921653687000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 481618 # number of writebacks +system.cpu.l2cache.tagsinuse 19824.270630 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2471683 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 910963647000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 436481 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3444665030 # number of cpu cycles simulated +system.cpu.numCycles 3403567782 # number of cpu cycles simulated system.cpu.num_insts 1495700521 # Number of instructions executed system.cpu.num_refs 533262345 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls |