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authorAli Saidi <Ali.Saidi@ARM.com>2012-01-25 17:19:50 +0000
committerAli Saidi <Ali.Saidi@ARM.com>2012-01-25 17:19:50 +0000
commita17dbdf8834b84f05a8f5154a74ac819fe8adc7c (patch)
tree8761136c790b84e20d6df2e84207eca3c553984b /tests/long/20.parser
parentbd55c9e2af7fd6c06af48a020c29cb33ba1ca3fc (diff)
downloadgem5-a17dbdf8834b84f05a8f5154a74ac819fe8adc7c.tar.xz
stats: Update stats for final tick and memory bandwidth patches
Diffstat (limited to 'tests/long/20.parser')
-rw-r--r--tests/long/20.parser/ref/arm/linux/o3-timing/config.ini7
-rwxr-xr-xtests/long/20.parser/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt19
-rw-r--r--tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini13
-rwxr-xr-xtests/long/20.parser/ref/arm/linux/simple-atomic/simerr1
-rwxr-xr-xtests/long/20.parser/ref/arm/linux/simple-atomic/simout16
-rw-r--r--tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt109
-rw-r--r--tests/long/20.parser/ref/arm/linux/simple-timing/config.ini11
-rwxr-xr-xtests/long/20.parser/ref/arm/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/20.parser/ref/arm/linux/simple-timing/simout16
-rw-r--r--tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt475
-rw-r--r--tests/long/20.parser/ref/x86/linux/o3-timing/config.ini12
-rwxr-xr-xtests/long/20.parser/ref/x86/linux/o3-timing/simout8
-rw-r--r--tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt19
-rw-r--r--tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini14
-rwxr-xr-xtests/long/20.parser/ref/x86/linux/simple-atomic/simout8
-rw-r--r--tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt19
-rw-r--r--tests/long/20.parser/ref/x86/linux/simple-timing/config.ini12
-rwxr-xr-xtests/long/20.parser/ref/x86/linux/simple-timing/simout8
-rw-r--r--tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt19
20 files changed, 427 insertions, 366 deletions
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
index bdd61e6fb..e2c071016 100644
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -19,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -478,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -520,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -530,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout
index a9de996c2..c61c0591a 100755
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 8 2012 22:11:51
-gem5 started Jan 9 2012 02:13:40
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:49:36
gem5 executing on zizzer
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
index 6e5455372..0cc2b2b8d 100644
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.274199 # Number of seconds simulated
sim_ticks 274198757500 # Number of ticks simulated
+final_tick 274198757500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 113676 # Simulator instruction rate (inst/s)
-host_tick_rate 54365362 # Simulator tick rate (ticks/s)
-host_mem_usage 225168 # Number of bytes of host memory used
-host_seconds 5043.63 # Real time elapsed on the host
+host_inst_rate 114096 # Simulator instruction rate (inst/s)
+host_tick_rate 54566255 # Simulator tick rate (ticks/s)
+host_mem_usage 225172 # Number of bytes of host memory used
+host_seconds 5025.06 # Real time elapsed on the host
sim_insts 573341162 # Number of instructions simulated
+system.physmem.bytes_read 15248640 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 230400 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 10960192 # Number of bytes written to this memory
+system.physmem.num_reads 238260 # Number of read requests responded to by this memory
+system.physmem.num_writes 171253 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 55611631 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 840266 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 39971706 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 95583336 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
index 8b55eca4f..cbe7d05b4 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
-cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/simerr b/tests/long/20.parser/ref/arm/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
index 7da122073..e26a927e8 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:53:21
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:54:41
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
index 6d10538b7..12a51d6fd 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 3887693 # Simulator instruction rate (inst/s)
-host_mem_usage 256484 # Number of bytes of host memory used
-host_seconds 146.87 # Real time elapsed on the host
-host_tick_rate 1977989899 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 570968176 # Number of instructions simulated
sim_seconds 0.290499 # Number of seconds simulated
sim_ticks 290498972000 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 3123764 # Simulator instruction rate (inst/s)
+host_tick_rate 1589318228 # Simulator tick rate (ticks/s)
+host_mem_usage 213568 # Number of bytes of host memory used
+host_seconds 182.78 # Real time elapsed on the host
+sim_insts 570968176 # Number of instructions simulated
+system.physmem.bytes_read 2489298238 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 2066445536 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 216067624 # Number of bytes written to this memory
+system.physmem.num_reads 641840242 # Number of read requests responded to by this memory
+system.physmem.num_writes 55727847 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 8569043191 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7113434935 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 743781028 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 9312824219 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 580997945 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 580997945 # Number of busy cycles
-system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
-system.cpu.num_fp_insts 16 # number of float instructions
-system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 15725605 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 570968176 # Number of instructions executed
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
+system.cpu.num_func_calls 15725605 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls
system.cpu.num_int_insts 470727703 # number of integer instructions
+system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 2465023721 # number of times the integer registers were read
system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written
-system.cpu.num_load_insts 126029556 # Number of load instructions
+system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 182890035 # number of memory refs
+system.cpu.num_load_insts 126029556 # Number of load instructions
system.cpu.num_store_insts 56860479 # Number of store instructions
-system.cpu.workload.num_syscalls 548 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 580997945 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
index 1771ad8e9..5a2d86232 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
-cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/20.parser/ref/arm/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/20.parser/ref/arm/linux/simple-timing/simout
index 3ee3b4f05..8c1353073 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:55:52
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:54:55
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
index 9f67dc057..f9d747bd5 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,280 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1138464 # Simulator instruction rate (inst/s)
-host_mem_usage 264236 # Number of bytes of host memory used
-host_seconds 499.83 # Real time elapsed on the host
-host_tick_rate 1444968716 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 569034848 # Number of instructions simulated
sim_seconds 0.722234 # Number of seconds simulated
sim_ticks 722234364000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 1488541 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 1488541 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 123740317 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 122957659 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 15502704000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.006325 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 782658 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 13154730000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.006325 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 782658 # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses 1488541 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 1488541 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 53883046 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 10028942000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.006568 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 356260 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 8960162000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.006568 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 356260 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 177979623 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 22417.457622 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 176840705 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 25531646000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.006399 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1138918 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 22114892000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.006399 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1138918 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 4065.490059 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.992551 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 177979623 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 22417.457622 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 176840705 # number of overall hits
-system.cpu.dcache.overall_miss_latency 25531646000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.006399 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1138918 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 22114892000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.006399 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1138918 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 1134822 # number of replacements
-system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use
-system.cpu.dcache.total_refs 179817787 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 1025440 # number of writebacks
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1518630 # Simulator instruction rate (inst/s)
+host_tick_rate 1927485562 # Simulator tick rate (ticks/s)
+host_mem_usage 222536 # Number of bytes of host memory used
+host_seconds 374.70 # Real time elapsed on the host
+sim_insts 569034848 # Number of instructions simulated
+system.physmem.bytes_read 14797056 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 188608 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 11027328 # Number of bytes written to this memory
+system.physmem.num_reads 231204 # Number of read requests responded to by this memory
+system.physmem.num_writes 172302 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 20487887 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 261145 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 15268351 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 35756238 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 516611385 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 548 # Number of system calls
+system.cpu.numCycles 1444468728 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 569034848 # Number of instructions executed
+system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
+system.cpu.num_func_calls 15725605 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls
+system.cpu.num_int_insts 470727703 # number of integer instructions
+system.cpu.num_fp_insts 16 # number of float instructions
+system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read
+system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_mem_refs 182890035 # number of memory refs
+system.cpu.num_load_insts 126029556 # Number of load instructions
+system.cpu.num_store_insts 56860479 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 1444468728 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 9788 # number of replacements
+system.cpu.icache.tagsinuse 984.426148 # Cycle average of tags in use
+system.cpu.icache.total_refs 516599864 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 984.426148 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.480677 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 516599864 # number of ReadReq hits
+system.cpu.icache.demand_hits 516599864 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 516599864 # number of overall hits
+system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses
+system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 11521 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 516611385 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 516611385 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 516611385 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 250505000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 516611385 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
-system.cpu.icache.demand_hits 516599864 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses
-system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses
+system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 250505000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 250505000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 250505000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000022 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 984.426148 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.480677 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses 516611385 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 516599864 # number of overall hits
-system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses
-system.cpu.icache.overall_misses 11521 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 250505000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 9788 # number of replacements
-system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 984.426148 # Cycle average of tags in use
-system.cpu.icache.total_refs 516599864 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 356260 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 1134822 # number of replacements
+system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use
+system.cpu.dcache.total_refs 179817787 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4065.490059 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.992551 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 122957659 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 53883046 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits 1488541 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits 1488541 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits 176840705 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 176840705 # number of overall hits
+system.cpu.dcache.ReadReq_misses 782658 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 356260 # number of WriteReq misses
+system.cpu.dcache.demand_misses 1138918 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 1138918 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 15502704000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 10028942000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 25531646000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 25531646000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 123740317 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses 1488541 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses 1488541 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 177979623 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 177979623 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.006325 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.006568 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.006399 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.006399 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 22417.457622 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 22417.457622 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 1025440 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 782658 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 356260 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 1138918 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 1138918 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 13154730000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 8960162000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 22114892000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 22114892000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.006325 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.006568 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.006399 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.006399 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 212089 # number of replacements
+system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1426644 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 6.145937 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 5849.157602 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 14594.006011 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.178502 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.445374 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 683006 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 1025440 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 236229 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 6241612000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.336920 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits 919235 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 919235 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 111173 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 120031 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801240000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336920 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 120031 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 794179 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 683006 # number of ReadReq hits
+system.cpu.l2cache.demand_misses 231204 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 231204 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 5780996000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.139985 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 111173 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 4446920000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139985 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 111173 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency 6241612000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 12022608000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 12022608000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 794179 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 1025440 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 1025440 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 6.145937 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses 356260 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 1150439 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 1150439 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.139985 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.336920 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.200970 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.200970 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 1150439 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 919235 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 12022608000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.200970 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 231204 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 172302 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 111173 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 120031 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 231204 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 231204 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 4446920000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801240000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 9248160000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 9248160000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139985 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336920 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.200970 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 231204 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 5849.157602 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 14594.006011 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.178502 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.445374 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 1150439 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.200970 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 919235 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 12022608000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.200970 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 231204 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 9248160000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.200970 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 231204 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 212089 # number of replacements
-system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1426644 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 172302 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1444468728 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 1444468728 # Number of busy cycles
-system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
-system.cpu.num_fp_insts 16 # number of float instructions
-system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 15725605 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 569034848 # Number of instructions executed
-system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
-system.cpu.num_int_insts 470727703 # number of integer instructions
-system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read
-system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written
-system.cpu.num_load_insts 126029556 # Number of load instructions
-system.cpu.num_mem_refs 182890035 # number of memory refs
-system.cpu.num_store_insts 56860479 # Number of store instructions
-system.cpu.workload.num_syscalls 548 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
index b2ef015f3..9cc27361f 100644
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,9 +502,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout
index f37768727..de72d963a 100755
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:58:28
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
index 556f62c4f..92ece0bed 100644
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.493912 # Number of seconds simulated
sim_ticks 493912286000 # Number of ticks simulated
+final_tick 493912286000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 108889 # Simulator instruction rate (inst/s)
-host_tick_rate 35174673 # Simulator tick rate (ticks/s)
-host_mem_usage 280548 # Number of bytes of host memory used
-host_seconds 14041.70 # Real time elapsed on the host
+host_inst_rate 145271 # Simulator instruction rate (inst/s)
+host_tick_rate 46927205 # Simulator tick rate (ticks/s)
+host_mem_usage 251468 # Number of bytes of host memory used
+host_seconds 10525.07 # Real time elapsed on the host
sim_insts 1528988756 # Number of instructions simulated
+system.physmem.bytes_read 37487424 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 347584 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 26320960 # Number of bytes written to this memory
+system.physmem.num_reads 585741 # Number of read requests responded to by this memory
+system.physmem.num_writes 411265 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 75898950 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 703736 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 53290758 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 129189708 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 987824573 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
index da3b012b0..b1057156b 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=X86TLB
@@ -67,9 +69,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
@@ -86,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
index d3e847fa3..b86175ab2 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:59:28
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
index c9073b3b2..4e0a10e13 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.885229 # Number of seconds simulated
sim_ticks 885229360000 # Number of ticks simulated
+final_tick 885229360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1063398 # Simulator instruction rate (inst/s)
-host_tick_rate 615669149 # Simulator tick rate (ticks/s)
-host_mem_usage 237896 # Number of bytes of host memory used
-host_seconds 1437.83 # Real time elapsed on the host
+host_inst_rate 2258239 # Simulator instruction rate (inst/s)
+host_tick_rate 1307438877 # Simulator tick rate (ticks/s)
+host_mem_usage 208528 # Number of bytes of host memory used
+host_seconds 677.07 # Real time elapsed on the host
sim_insts 1528988757 # Number of instructions simulated
+system.physmem.bytes_read 10832432532 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 8546776872 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 991849460 # Number of bytes written to this memory
+system.physmem.num_reads 1452449298 # Number of read requests responded to by this memory
+system.physmem.num_writes 149160201 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 12236865406 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 9654872803 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1120443475 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 13357308881 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 1770458721 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
index e63456bf2..c570a48d2 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -170,9 +172,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
@@ -189,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
index 268de88f4..a297c4bc8 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 07:10:56
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
index a96327ae0..28d09902a 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.658730 # Number of seconds simulated
sim_ticks 1658729604000 # Number of ticks simulated
+final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 746220 # Simulator instruction rate (inst/s)
-host_tick_rate 809539282 # Simulator tick rate (ticks/s)
-host_mem_usage 246668 # Number of bytes of host memory used
-host_seconds 2048.98 # Real time elapsed on the host
+host_inst_rate 1326745 # Simulator instruction rate (inst/s)
+host_tick_rate 1439324936 # Simulator tick rate (ticks/s)
+host_mem_usage 217512 # Number of bytes of host memory used
+host_seconds 1152.44 # Real time elapsed on the host
sim_insts 1528988757 # Number of instructions simulated
+system.physmem.bytes_read 37094976 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 148544 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 26349376 # Number of bytes written to this memory
+system.physmem.num_reads 579609 # Number of read requests responded to by this memory
+system.physmem.num_writes 411709 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 22363486 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 89553 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 15885275 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 38248761 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 3317459208 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started