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authorGabe Black <gblack@eecs.umich.edu>2009-02-25 10:16:29 -0800
committerGabe Black <gblack@eecs.umich.edu>2009-02-25 10:16:29 -0800
commitf02df8cb7400d59c338abf44d2f7adfc9a665fa0 (patch)
treee14436b2acc6262858654cab2fdd91c69093514d /tests/long/20.parser
parent40fdba2454c219902db7ad1abd28593de8611c2b (diff)
downloadgem5-f02df8cb7400d59c338abf44d2f7adfc9a665fa0.tar.xz
X86: Update stats for in place TLB miss handling.
Diffstat (limited to 'tests/long/20.parser')
-rwxr-xr-xtests/long/20.parser/ref/x86/linux/simple-atomic/simout10
-rw-r--r--tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt16
-rwxr-xr-xtests/long/20.parser/ref/x86/linux/simple-timing/simout10
-rw-r--r--tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt42
4 files changed, 39 insertions, 39 deletions
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
index 0154cb675..6f49cefcf 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:19:15
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 01:09:31
-M5 executing on zizzer
+M5 compiled Feb 23 2009 23:45:19
+M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
+M5 started Feb 23 2009 23:48:10
+M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py long/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -74,4 +74,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 868682305500 because target called exit()
+Exiting @ tick 868476152500 because target called exit()
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
index 2072caa4b..a32bcd78e 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -1,18 +1,18 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1649324 # Simulator instruction rate (inst/s)
-host_mem_usage 201208 # Number of bytes of host memory used
-host_seconds 906.72 # Real time elapsed on the host
-host_tick_rate 958044415 # Simulator tick rate (ticks/s)
+host_inst_rate 954040 # Simulator instruction rate (inst/s)
+host_mem_usage 200820 # Number of bytes of host memory used
+host_seconds 1567.53 # Real time elapsed on the host
+host_tick_rate 554042856 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495482356 # Number of instructions simulated
-sim_seconds 0.868682 # Number of seconds simulated
-sim_ticks 868682305500 # Number of ticks simulated
+sim_seconds 0.868476 # Number of seconds simulated
+sim_ticks 868476152500 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1737364612 # number of cpu cycles simulated
+system.cpu.numCycles 1736952306 # number of cpu cycles simulated
system.cpu.num_insts 1495482356 # Number of instructions executed
-system.cpu.num_refs 533548971 # Number of memory references
+system.cpu.num_refs 533262337 # Number of memory references
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
index 6d4d2b6e7..bc32d8a8e 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:19:15
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 01:11:36
-M5 executing on zizzer
+M5 compiled Feb 23 2009 23:45:19
+M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
+M5 started Feb 23 2009 23:48:10
+M5 executing on tater
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py long/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -74,4 +74,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 2391369984000 because target called exit()
+Exiting @ tick 2390957741000 because target called exit()
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
index 923ce5951..c30384fe4 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1421036 # Simulator instruction rate (inst/s)
-host_mem_usage 208620 # Number of bytes of host memory used
-host_seconds 1052.39 # Real time elapsed on the host
-host_tick_rate 2272325062 # Simulator tick rate (ticks/s)
+host_inst_rate 732305 # Simulator instruction rate (inst/s)
+host_mem_usage 208264 # Number of bytes of host memory used
+host_seconds 2042.16 # Real time elapsed on the host
+host_tick_rate 1170799737 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495482356 # Number of instructions simulated
-sim_seconds 2.391370 # Number of seconds simulated
-sim_ticks 2391369984000 # Number of ticks simulated
+sim_seconds 2.390958 # Number of seconds simulated
+sim_ticks 2390957741000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 384102182 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency
@@ -67,14 +67,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0
system.cpu.dcache.replacements 2513875 # number of replacements
system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4086.151068 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4086.149487 # Cycle average of tags in use
system.cpu.dcache.total_refs 530744411 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 12270576000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 12270471000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1463913 # number of writebacks
-system.cpu.icache.ReadReq_accesses 1737364550 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses 1736952307 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 48415.215073 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 45415.215073 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1737361737 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits 1736949494 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 136192000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 2813 # number of ReadReq misses
@@ -83,16 +83,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # ms
system.cpu.icache.ReadReq_mshr_misses 2813 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 617618.818699 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 617472.269463 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1737364550 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses 1736952307 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 48415.215073 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1737361737 # number of demand (read+write) hits
+system.cpu.icache.demand_hits 1736949494 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 136192000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_misses 2813 # number of demand (read+write) misses
@@ -103,11 +103,11 @@ system.cpu.icache.demand_mshr_misses 2813 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1737364550 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses 1736952307 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 48415.215073 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1737361737 # number of overall hits
+system.cpu.icache.overall_hits 1736949494 # number of overall hits
system.cpu.icache.overall_miss_latency 136192000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_misses 2813 # number of overall misses
@@ -120,8 +120,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 1253 # number of replacements
system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 873.846977 # Cycle average of tags in use
-system.cpu.icache.total_refs 1737361737 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 873.828248 # Cycle average of tags in use
+system.cpu.icache.total_refs 1736949494 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
@@ -194,14 +194,14 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0
system.cpu.l2cache.replacements 663512 # number of replacements
system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 17171.685875 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 17171.450430 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 1313098367000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.warmup_cycle 1312958337000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 481430 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 4782739968 # number of cpu cycles simulated
+system.cpu.numCycles 4781915482 # number of cpu cycles simulated
system.cpu.num_insts 1495482356 # Number of instructions executed
-system.cpu.num_refs 533548971 # Number of memory references
+system.cpu.num_refs 533262337 # Number of memory references
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
---------- End Simulation Statistics ----------