diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-01-18 16:30:06 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-01-18 16:30:06 -0600 |
| commit | f7885b8f260ca11c2f4a405525d9fc4e554f41a8 (patch) | |
| tree | 7843d9030dd422473d7efd5a4e2a0fd787e2b7f8 /tests/long/20.parser | |
| parent | 9b67f3723e48efdd0a0b640ff82cfcf8aad3a659 (diff) | |
| download | gem5-f7885b8f260ca11c2f4a405525d9fc4e554f41a8.tar.xz | |
ARM/O3: Add regressions for ARM w/ O3 CPU.
Diffstat (limited to 'tests/long/20.parser')
| -rw-r--r-- | tests/long/20.parser/ref/arm/linux/o3-timing/config.ini | 517 | ||||
| -rwxr-xr-x | tests/long/20.parser/ref/arm/linux/o3-timing/simerr | 85 | ||||
| -rwxr-xr-x | tests/long/20.parser/ref/arm/linux/o3-timing/simout | 75 | ||||
| -rw-r--r-- | tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt | 489 |
4 files changed, 1166 insertions, 0 deletions
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini new file mode 100644 index 000000000..5f7dcc6cf --- /dev/null +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini @@ -0,0 +1,517 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList4.opList + +[system.cpu.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList6.opList + +[system.cpu.fuPool.FUList6.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=parser 2.1.dict -batch +cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser +gid=100 +input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=114600000000 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/20.parser/ref/arm/linux/o3-timing/simerr new file mode 100755 index 000000000..04a78633e --- /dev/null +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simerr @@ -0,0 +1,85 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0x2. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0x2. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0x402807b6. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0x6. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0x6. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0x6. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0x6. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xbeffffee. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0x403387de. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xa. +For more information see: http://www.m5sim.org/warn/55f199fd +warn: Bad interworking branch address 0xa. +For more information see: http://www.m5sim.org/warn/55f199fd +hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout new file mode 100755 index 000000000..7fcfd6a75 --- /dev/null +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout @@ -0,0 +1,75 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jan 11 2011 18:16:01 +M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip +M5 started Jan 12 2011 03:20:30 +M5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + + Reading the dictionary files: ************************************************* + + +Welcome to the Link Parser -- Version 2.1 + + Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley + +Processing sentences in batch mode + +info: Increasing stack size by one page. +Echoing of input sentence turned on. +* as had expected the party to be a success , it was a success +* do you know where John 's +* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. +* how fast the program is it +* I am wondering whether to invite to the party +* I gave him for his birthday it +* I thought terrible after our discussion +* I wonder how much money have you earned +* Janet who is an expert on dogs helped me choose one +* she interviewed more programmers than was hired +* such flowers are found chiefly particularly in Europe +* the dogs some of which were very large ran after the man +* the man whom I play tennis is here +* there is going to be an important meeting January +* to pretend that our program is usable in its current form would be happy +* we're thinking about going to a movie this theater +* which dog you said you chased +- also invited to the meeting were several prominent scientists +- he ran home so quickly that his mother could hardly believe he had called from school +- so many people attended that they spilled over into several neighboring fields +- voting in favor of the bill were 36 Republicans and 4 moderate Democrats +: Grace may not be possible to fix the problem + any program as good as ours should be useful + biochemically , I think the experiment has a lot of problems + Fred has had five years of experience as a programmer + he is looking for another job + how did John do it + how many more people do you think will come + how much more spilled + I have more money than John has time + I made it clear that I was angry + I wonder how John did it + I wonder how much more quickly he ran + invite John and whoever else you want to invite + it is easier to ignore the problem than it is to solve it + many who initially supported Thomas later changed their minds + neither Mary nor Louise are coming to the party + she interviewed more programmers than were hired + telling Joe that Sue was coming to the party would create a real problem + the man with whom I play tennis is here + there is a dog in the park + this is not the man we know and love + we like to eat at restaurants , usually on weekends + what did John say he thought you should do + about 2 million people attended + the five best costumes got prizes +No errors! +Exiting @ tick 365535797000 because target called exit() diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt new file mode 100644 index 000000000..b9adedb70 --- /dev/null +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -0,0 +1,489 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 95936 # Simulator instruction rate (inst/s) +host_mem_usage 255716 # Number of bytes of host memory used +host_seconds 5851.87 # Real time elapsed on the host +host_tick_rate 62464794 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 561403855 # Number of instructions simulated +sim_seconds 0.365536 # Number of seconds simulated +sim_ticks 365535797000 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 140412857 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 174405829 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 15516134 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 191856696 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 191856696 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 110089780 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 3543910 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle::samples 660408748 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.850085 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.259950 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 341979114 51.78% 51.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 195474584 29.60% 81.38% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 65236254 9.88% 91.26% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 25100650 3.80% 95.06% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 18282819 2.77% 97.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 7231568 1.10% 98.92% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 2404526 0.36% 99.29% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 1155323 0.17% 99.46% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 3543910 0.54% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 660408748 # Number of insts commited each cycle +system.cpu.commit.COM:count 561403855 # Number of instructions committed +system.cpu.commit.COM:loads 128127024 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 184987501 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 27361456 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 561403855 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 157189 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 399600068 # The number of squashed insts skipped by commit +system.cpu.committedInsts 561403855 # Number of Instructions Simulated +system.cpu.committedInsts_total 561403855 # Number of Instructions Simulated +system.cpu.cpi 1.302220 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.302220 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 149781892 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 10115.689557 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6757.918127 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 148783591 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 10098503000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.006665 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 998301 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 174053 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 5570200500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005503 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 824248 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 55727847 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 14769.740800 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13602.051977 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 54444667 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 18952236000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.023026 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1283180 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 935759 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 4725638500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006234 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 347421 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 173.452238 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 205509739 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 12733.281145 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8787.327308 # average overall mshr miss latency +system.cpu.dcache.demand_hits 203228258 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 29050739000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.011102 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2281481 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1109812 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 10295839000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005701 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1171669 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.992538 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4065.435193 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 205509739 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 12733.281145 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8787.327308 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 203228258 # number of overall hits +system.cpu.dcache.overall_miss_latency 29050739000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.011102 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2281481 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1109812 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 10295839000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005701 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1171669 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 1167571 # number of replacements +system.cpu.dcache.sampled_refs 1171667 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4065.435193 # Cycle average of tags in use +system.cpu.dcache.total_refs 203228263 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 6053773000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 1048319 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 23914899 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 1082691365 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 293791436 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 339619753 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 66259738 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 3082660 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 191856696 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 122785155 # Number of cache lines fetched +system.cpu.fetch.Cycles 351913139 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 3732953 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 938955668 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 5443516 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 27647770 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.262432 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 122785155 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 140412857 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.284355 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 726668486 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.538402 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.455586 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 375480392 51.67% 51.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 167711007 23.08% 74.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28511073 3.92% 78.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34539499 4.75% 83.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26732700 3.68% 87.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 10963415 1.51% 88.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11441350 1.57% 90.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11151746 1.53% 91.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 60137304 8.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 726668486 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 122785155 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 13335.070892 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 9658.160050 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 122768369 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 223842500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000137 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 16786 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 916 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 153275000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000129 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 15870 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 7736.852092 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 122785155 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 13335.070892 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 9658.160050 # average overall mshr miss latency +system.cpu.icache.demand_hits 122768369 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 223842500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000137 # miss rate for demand accesses +system.cpu.icache.demand_misses 16786 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 916 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 153275000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000129 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 15870 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.542928 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1111.916228 # Average occupied blocks per context +system.cpu.icache.overall_accesses 122785155 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 13335.070892 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 9658.160050 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 122768369 # number of overall hits +system.cpu.icache.overall_miss_latency 223842500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000137 # miss rate for overall accesses +system.cpu.icache.overall_misses 16786 # number of overall misses +system.cpu.icache.overall_mshr_hits 916 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 153275000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000129 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 15870 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 14020 # number of replacements +system.cpu.icache.sampled_refs 15868 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1111.916228 # Cycle average of tags in use +system.cpu.icache.total_refs 122768369 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idleCycles 4403109 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 125406817 # Number of branches executed +system.cpu.iew.EXEC:nop 0 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.996154 # Inst execution rate +system.cpu.iew.EXEC:refs 229537979 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 71989836 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 715317405 # num instructions consuming a value +system.cpu.iew.WB:count 674936623 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.509545 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 364486134 # num instructions producing a value +system.cpu.iew.WB:rate 0.923215 # insts written-back per cycle +system.cpu.iew.WB:sent 715720315 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 30103584 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2644883 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 200154824 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 162257 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 12097440 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 140083731 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 960991852 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 157548143 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 31983856 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 728259959 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 123835 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 3633 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 66259738 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 187555 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 4454393 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 9891 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 352056 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 12768 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 72027799 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 83223254 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 352056 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 15636111 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 14467473 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.767919 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.767919 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 514982916 67.74% 67.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 348808 0.05% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 120 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 162349838 21.35% 89.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 82562130 10.86% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 760243815 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 11461228 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.015076 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 133776 1.17% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 5928179 51.72% 52.89% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 5399273 47.11% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 726668486 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.046204 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.384447 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 339626130 46.74% 46.74% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 195069580 26.84% 73.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 101922937 14.03% 87.61% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 40650184 5.59% 93.20% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 24674774 3.40% 96.60% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 15399691 2.12% 98.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 3388059 0.47% 99.18% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 4145144 0.57% 99.75% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 1791987 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 726668486 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.039903 # Inst issue rate +system.cpu.iq.iqInstsAdded 960829595 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 760243815 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 162257 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 389023744 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 7997557 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 5068 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 710003502 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses 347847 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34254.310886 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31004.170745 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 228324 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 4094178000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.343608 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 119523 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3705711500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.343608 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 119523 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 839688 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34183.859863 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.526653 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 724943 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 3922427000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.136652 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 114745 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 30 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 3558405000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.136616 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 114715 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits +system.cpu.l2cache.Writeback_accesses 1048319 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1048319 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 6.336020 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 1187535 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34219.803814 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31011.691101 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 953267 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 8016605000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.197273 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 234268 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 30 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 7264116500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.197247 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 234238 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.185686 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.450094 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 6084.559967 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14748.682079 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 1187535 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34219.803814 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31011.691101 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 953267 # number of overall hits +system.cpu.l2cache.overall_miss_latency 8016605000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.197273 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 234268 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 30 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 7264116500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.197247 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 234238 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements 215168 # number of replacements +system.cpu.l2cache.sampled_refs 235364 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 20833.242046 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1491271 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 262458362000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 171581 # number of writebacks +system.cpu.memDep0.conflictingLoads 60170710 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 74734099 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 200154824 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 140083731 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 731071595 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 7125233 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 435368498 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 5221350 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 309286671 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 9288405 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 16 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 2644676144 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 1043986494 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 713690265 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 326862324 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 66259738 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 15428382 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 278321764 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 1706138 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 233255 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 48704887 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 185624 # count of temporary serializing insts renamed +system.cpu.timesIdled 93433 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 548 # Number of system calls + +---------- End Simulation Statistics ---------- |