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author | Gabe Black <gblack@eecs.umich.edu> | 2012-01-28 07:24:01 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2012-01-28 07:24:01 -0800 |
commit | c3d41a2def15cdaf2ac3984315f452dacc6a0884 (patch) | |
tree | 5324ebec3add54b934a841eee901983ac3463a7f /tests/long/30.eon/ref/alpha/tru64/o3-timing | |
parent | da2a4acc26ba264c3c4a12495776fd6a1c4fb133 (diff) | |
parent | 4acca8a0536d4445ed25b67edf571ae460446ab9 (diff) | |
download | gem5-c3d41a2def15cdaf2ac3984315f452dacc6a0884.tar.xz |
Merge with the main repo.
--HG--
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
Diffstat (limited to 'tests/long/30.eon/ref/alpha/tru64/o3-timing')
-rw-r--r-- | tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini | 8 | ||||
-rwxr-xr-x | tests/long/30.eon/ref/alpha/tru64/o3-timing/simout | 6 | ||||
-rw-r--r-- | tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 18 |
3 files changed, 21 insertions, 11 deletions
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 01d03e5c5..0fce2844b 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ type=System children=cpu membus physmem mem_mode=atomic memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -18,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU @@ -477,7 +479,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] +mem_side=system.membus.port[2] [system.cpu.toL2Bus] type=Bus @@ -519,7 +521,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -529,5 +531,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[0] +port=system.membus.port[1] diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index 46133d214..137fd0ee8 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 16:10:02 -gem5 started Aug 20 2011 16:10:09 +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 05:24:12 gem5 executing on zizzer command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index f27e3deec..28785f469 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -2,12 +2,22 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.089480 # Number of seconds simulated sim_ticks 89480174500 # Number of ticks simulated +final_tick 89480174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168732 # Simulator instruction rate (inst/s) -host_tick_rate 40200085 # Simulator tick rate (ticks/s) -host_mem_usage 211620 # Number of bytes of host memory used -host_seconds 2225.87 # Real time elapsed on the host +host_inst_rate 190161 # Simulator instruction rate (inst/s) +host_tick_rate 45305657 # Simulator tick rate (ticks/s) +host_mem_usage 214676 # Number of bytes of host memory used +host_seconds 1975.03 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated +system.physmem.bytes_read 475840 # Number of bytes read from this memory +system.physmem.bytes_inst_read 219968 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 7435 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 5317826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 2458288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 5317826 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv |