diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
commit | a51e2fd8bd581d45f8a87874c9a6680f99d11e24 (patch) | |
tree | 8de4626b115b234de0962cc04d32e15b6eb0fa3a /tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt | |
parent | e7e2d5ce9072808d94d5fe399e6c4262d92b7923 (diff) | |
download | gem5-a51e2fd8bd581d45f8a87874c9a6680f99d11e24.tar.xz |
Stats: Update the stats.
--HG--
extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
Diffstat (limited to 'tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt')
-rw-r--r-- | tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt | 34 |
1 files changed, 25 insertions, 9 deletions
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt index 2e2beec40..e32cacf16 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,18 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 828868 # Simulator instruction rate (inst/s) -host_mem_usage 151076 # Number of bytes of host memory used -host_seconds 480.97 # Real time elapsed on the host -host_tick_rate 414433819 # Simulator tick rate (ticks/s) +host_inst_rate 2526947 # Simulator instruction rate (inst/s) +host_mem_usage 181828 # Number of bytes of host memory used +host_seconds 157.77 # Real time elapsed on the host +host_tick_rate 1263471125 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 398664597 # Number of instructions simulated +sim_insts 398664595 # Number of instructions simulated sim_seconds 0.199332 # Number of seconds simulated -sim_ticks 199332298000 # Number of ticks simulated +sim_ticks 199332411500 # Number of ticks simulated +system.cpu.dtb.accesses 168275274 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 168275218 # DTB hits +system.cpu.dtb.misses 56 # DTB misses +system.cpu.dtb.read_accesses 94754510 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 94754489 # DTB read hits +system.cpu.dtb.read_misses 21 # DTB read misses +system.cpu.dtb.write_accesses 73520764 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 73520729 # DTB write hits +system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 398664824 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 398664651 # ITB hits +system.cpu.itb.misses 173 # ITB misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 398664597 # number of cpu cycles simulated -system.cpu.num_insts 398664597 # Number of instructions executed -system.cpu.num_refs 174183399 # Number of memory references +system.cpu.numCycles 398664824 # number of cpu cycles simulated +system.cpu.num_insts 398664595 # Number of instructions executed +system.cpu.num_refs 174183453 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- |