Bus: Update the stats for the recent bus fix.

--HG--
extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407

1 files changed, 48 insertions, 48 deletions

diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt
index 6d3f9def2..f6e3615e0 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 850841                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 157124                       # Number of bytes of host memory used
-host_seconds                                   468.55                       # Real time elapsed on the host
-host_tick_rate                             1210368735                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 948947                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204452                       # Number of bytes of host memory used
+host_seconds                                   420.11                       # Real time elapsed on the host
+host_tick_rate                             1349967290                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   398664609                       # Number of instructions simulated
-sim_seconds                                  0.567123                       # Number of seconds simulated
-sim_ticks                                567123353000                       # Number of ticks simulated
+sim_seconds                                  0.567139                       # Number of seconds simulated
+sim_ticks                                567138642000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           94754490                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 23522.105263                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21522.105263                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 25398.947368                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22398.947368                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               94753540                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency       22346000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency       24129000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.000010                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                  950                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     20446000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency     21279000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses             950                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          73520730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency        25000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        23000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency        27000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency        24000                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits              73517416                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency      82850000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency      89478000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.000045                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses                3314                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency     76222000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     79536000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000045                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses           3314                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           168275220                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 24670.731707                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 22670.731707                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 26643.292683                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23643.292683                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits               168270956                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       105196000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency       113607000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                  4264                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency     96668000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    100815000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses             4264                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses          168275220                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 24670.731707                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 22670.731707                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 26643.292683                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23643.292683                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits              168270956                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      105196000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency      113607000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses                 4264                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency     96668000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    100815000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses            4264                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                    764                       # number of replacements
 system.cpu.dcache.sampled_refs                   4152                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               3289.454246                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               3289.418113                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                168271068                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                      625                       # number of writebacks
@@ -93,13 +93,13 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                    73520730                       # DTB write hits
 system.cpu.dtb.write_misses                        35                       # DTB write misses
 system.cpu.icache.ReadReq_accesses          398664666                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 23471.004628                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 21471.004628                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 25343.588347                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 22343.588347                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits              398660993                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       86209000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency       93087000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000009                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                 3673                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency     78863000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     82068000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000009                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses            3673                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses           398664666                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 23471.004628                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 21471.004628                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 25343.588347                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 22343.588347                       # average overall mshr miss latency
 system.cpu.icache.demand_hits               398660993                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        86209000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency        93087000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000009                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                  3673                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     78863000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     82068000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000009                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses             3673                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses          398664666                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 23471.004628                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 21471.004628                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 25343.588347                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 22343.588347                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits              398660993                       # number of overall hits
-system.cpu.icache.overall_miss_latency       86209000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency       93087000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000009                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                 3673                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     78863000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     82068000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000009                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses            3673                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                   1769                       # number of replacements
 system.cpu.icache.sampled_refs                   3673                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1795.369921                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1795.354000                       # Cycle average of tags in use
 system.cpu.icache.total_refs                398660993                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -160,28 +160,28 @@ system.cpu.itb.acv                                  0                       # IT
 system.cpu.itb.hits                         398664666                       # ITB hits
 system.cpu.itb.misses                             173                       # ITB misses
 system.cpu.l2cache.ReadExReq_accesses            3202                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency        22000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        23000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        11000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency     70444000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     73646000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_misses              3202                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_mshr_miss_latency     35222000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_misses         3202                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses              4623                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        22000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency        23000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        11000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                   585                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency      88836000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency      92874000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.873459                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses                4038                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency     44418000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.873459                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses           4038                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_accesses            112                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        22000                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency        23000                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        11000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency      2464000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency      2576000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_misses              112                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency      1232000                       # number of UpgradeReq MSHR miss cycles
@@ -198,10 +198,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses               7825                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        22000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency        23000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                    585                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      159280000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency      166520000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.925240                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                 7240                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
@@ -212,11 +212,11 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses              7825                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        22000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        23000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                   585                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     159280000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency     166520000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.925240                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                7240                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
@@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements                    15                       # number of replacements
 system.cpu.l2cache.sampled_refs                  4491                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              3714.863490                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              3714.818787                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                     540                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       1134246706                       # number of cpu cycles simulated
+system.cpu.numCycles                       1134277284                       # number of cpu cycles simulated
 system.cpu.num_insts                        398664609                       # Number of instructions executed
 system.cpu.num_refs                         174183455                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             215                       # Number of system calls