Regression: Update stats for cache changes.

--HG--
extra : convert_revision : 005672e722dec00cb4c38501b5189b4eb7515ca1

1 files changed, 101 insertions, 80 deletions

diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt
index 28c7cc183..5d80e04f0 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 579996                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 156556                       # Number of bytes of host memory used
-host_seconds                                   687.36                       # Real time elapsed on the host
-host_tick_rate                              824955659                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1477024                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 207136                       # Number of bytes of host memory used
+host_seconds                                   269.91                       # Real time elapsed on the host
+host_tick_rate                             2101151515                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   398664611                       # Number of instructions simulated
-sim_seconds                                  0.567040                       # Number of seconds simulated
-sim_ticks                                567040254000                       # Number of ticks simulated
+sim_seconds                                  0.567124                       # Number of seconds simulated
+sim_ticks                                567123959000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           94754490                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 13741.052632                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12741.052632                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 24216.842105                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22216.842105                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               94753540                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency       13054000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency       23006000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.000010                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                  950                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     12104000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency     21106000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses             950                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          73520730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 13962.523423                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12962.523423                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              73517528                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency      44708000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000044                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                3202                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency     41506000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000044                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           3202                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency        25000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency        23000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              73517416                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency      82850000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.000045                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses                3314                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency     76222000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000045                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses           3314                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs               40527.713873                       # Average number of references to valid blocks.
@@ -37,31 +37,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           168275220                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 13911.849711                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 12911.849711                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               168271068                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency        57762000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_avg_miss_latency 24825.515947                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 22825.515947                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               168270956                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency       105856000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  4152                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses                  4264                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency     53610000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency     97328000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             4152                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses             4264                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses          168275220                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 13911.849711                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 12911.849711                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 24825.515947                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 22825.515947                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              168271068                       # number of overall hits
-system.cpu.dcache.overall_miss_latency       57762000                       # number of overall miss cycles
+system.cpu.dcache.overall_hits              168270956                       # number of overall hits
+system.cpu.dcache.overall_miss_latency      105856000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 4152                       # number of overall misses
+system.cpu.dcache.overall_misses                 4264                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency     53610000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency     97328000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            4152                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses            4264                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                    764                       # number of replacements
 system.cpu.dcache.sampled_refs                   4152                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               3289.654807                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               3289.454030                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                168271068                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                      625                       # number of writebacks
 system.cpu.icache.ReadReq_accesses          398664612                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 13745.167438                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12745.167438                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 23471.004628                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 21471.004628                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits              398660939                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       50486000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency       86209000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000009                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                 3673                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency     46813000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     78863000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000009                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses            3673                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses           398664612                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 13745.167438                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12745.167438                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 23471.004628                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 21471.004628                       # average overall mshr miss latency
 system.cpu.icache.demand_hits               398660939                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        50486000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency        86209000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000009                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                  3673                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     46813000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     78863000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000009                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses             3673                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses          398664612                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 13745.167438                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12745.167438                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 23471.004628                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 21471.004628                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits              398660939                       # number of overall hits
-system.cpu.icache.overall_miss_latency       50486000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency       86209000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000009                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                 3673                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     46813000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     78863000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000009                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses            3673                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -138,57 +138,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                   1769                       # number of replacements
 system.cpu.icache.sampled_refs                   3673                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1795.458615                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1795.369888                       # Cycle average of tags in use
 system.cpu.icache.total_refs                398660939                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses              7825                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency        13000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_accesses            3202                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency        22000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        11000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency     70444000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses              3202                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     35222000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses         3202                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses              4623                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency        22000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        11000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                   651                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency      93262000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.916805                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                7174                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     78914000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.916805                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses           7174                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_hits                   530                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency      90046000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.885356                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                4093                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency     45023000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.885356                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses           4093                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses            112                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency        22000                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        11000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency      2464000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses              112                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency      1232000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses          112                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.Writeback_accesses             625                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits                 625                       # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate              1                       # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses               625                       # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate            1                       # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses          625                       # number of Writeback MSHR misses
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.177865                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.128109                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses               7825                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency        13000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency        22000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                    651                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency       93262000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.916805                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 7174                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                    530                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency      160490000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.932268                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                 7295                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency     78914000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.916805                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            7174                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency     80245000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.932268                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses            7295                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses              8450                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency        13000                       # average overall miss latency
+system.cpu.l2cache.overall_accesses              7825                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency        22000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                  1276                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency      93262000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.848994                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                7174                       # number of overall misses
+system.cpu.l2cache.overall_hits                   530                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency     160490000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.932268                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                7295                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency     78914000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.848994                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           7174                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency     80245000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.932268                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses           7295                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -200,15 +221,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued            0
 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                  7174                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                     6                       # number of replacements
+system.cpu.l2cache.sampled_refs                  3981                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              6483.455048                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    1276                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              3355.056948                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                     510                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                     567040254000                       # number of cpu cycles simulated
+system.cpu.numCycles                     567123959000                       # number of cpu cycles simulated
 system.cpu.num_insts                        398664611                       # Number of instructions executed
 system.cpu.num_refs                         174183401                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             215                       # Number of system calls