diff options
author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
---|---|---|
committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
commit | 13a15c55a40e86e5f3948a387fb5e50b9a1cdccf (patch) | |
tree | 762286677b3170cf9a7fb348f44e74a276230d6c /tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt | |
parent | e9185363804489ce2b84d50fe77ed94f3a5f1e01 (diff) | |
download | gem5-13a15c55a40e86e5f3948a387fb5e50b9a1cdccf.tar.xz |
stats: update stats for previous cset
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
Diffstat (limited to 'tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt')
-rw-r--r-- | tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt | 139 |
1 files changed, 65 insertions, 74 deletions
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 576c22b47..137741cba 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1188061 # Simulator instruction rate (inst/s) -host_mem_usage 213244 # Number of bytes of host memory used -host_seconds 335.56 # Real time elapsed on the host -host_tick_rate 1690751695 # Simulator tick rate (ticks/s) +host_inst_rate 1240949 # Simulator instruction rate (inst/s) +host_mem_usage 199424 # Number of bytes of host memory used +host_seconds 321.26 # Real time elapsed on the host +host_tick_rate 1766004728 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated -sim_seconds 0.567347 # Number of seconds simulated -sim_ticks 567347489000 # Number of ticks simulated +sim_seconds 0.567343 # Number of seconds simulated +sim_ticks 567343170000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency @@ -19,15 +19,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 45436000 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55961.075070 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52961.075070 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73517493 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 181146000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 55212.991880 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52212.991880 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73517528 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 176792000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 3237 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 171435000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 167186000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3237 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 54796.274182 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51796.274182 # average overall mshr miss latency -system.cpu.dcache.demand_hits 168271033 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 229432000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 54209.537572 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51209.537572 # average overall mshr miss latency +system.cpu.dcache.demand_hits 168271068 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 225078000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_misses 4187 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 216871000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 212622000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4187 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.802957 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 3288.911680 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 3288.912598 # Average occupied blocks per context system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 54796.274182 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51796.274182 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 54209.537572 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51209.537572 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 168271033 # number of overall hits -system.cpu.dcache.overall_miss_latency 229432000 # number of overall miss cycles +system.cpu.dcache.overall_hits 168271068 # number of overall hits +system.cpu.dcache.overall_miss_latency 225078000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_misses 4187 # number of overall misses +system.cpu.dcache.overall_misses 4152 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 216871000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 212622000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4187 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3288.911680 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3288.912598 # Cycle average of tags in use system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 625 # number of writebacks +system.cpu.dcache.writebacks 649 # number of writebacks system.cpu.dtb.data_accesses 168275276 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 168275220 # DTB hits @@ -122,7 +122,7 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.occ_%::0 0.876529 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1795.130856 # Average occupied blocks per context +system.cpu.icache.occ_blocks::0 1795.131074 # Average occupied blocks per context system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 1769 # number of replacements system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1795.130856 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1795.131074 # Cycle average of tags in use system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -164,13 +164,13 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 166348000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.999063 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 3199 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 127960000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999063 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 3199 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 163384000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.981262 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 3142 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 125680000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981262 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 3142 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency @@ -181,20 +181,11 @@ system.cpu.l2cache.ReadReq_misses 4038 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 35 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1820000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 35 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1400000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 35 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits +system.cpu.l2cache.Writeback_accesses 649 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 649 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.125220 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.143482 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -203,44 +194,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 588 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 376324000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.924856 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7237 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 645 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 373360000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.917572 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7180 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 289480000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.924856 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7237 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 287200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.917572 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7180 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.103673 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.011078 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 3397.172145 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 362.997313 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.103674 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.011338 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 3397.175455 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 371.536808 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 588 # number of overall hits -system.cpu.l2cache.overall_miss_latency 376324000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.924856 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7237 # number of overall misses +system.cpu.l2cache.overall_hits 645 # number of overall hits +system.cpu.l2cache.overall_miss_latency 373360000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.917572 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7180 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 289480000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.924856 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7237 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 287200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.917572 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7180 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 14 # number of replacements -system.cpu.l2cache.sampled_refs 4544 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 13 # number of replacements +system.cpu.l2cache.sampled_refs 4572 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3760.169458 # Cycle average of tags in use -system.cpu.l2cache.total_refs 569 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3768.712262 # Cycle average of tags in use +system.cpu.l2cache.total_refs 656 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1134694978 # number of cpu cycles simulated +system.cpu.numCycles 1134686340 # number of cpu cycles simulated system.cpu.num_insts 398664609 # Number of instructions executed system.cpu.num_refs 174183455 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls |