diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-03-11 19:02:06 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-03-11 19:02:06 -0400 |
| commit | 431dec5cd5b6643ba964cc38ed7b053cdaca11c5 (patch) | |
| tree | e9de8dd5f8754202e83f582c15a1188a0f39aba3 /tests/long/30.eon/ref/alpha/tru64/simple-timing | |
| parent | c3f3c56237d25eade43ccac3e0782617ed8c7272 (diff) | |
| download | gem5-431dec5cd5b6643ba964cc38ed7b053cdaca11c5.tar.xz | |
eon is a tru64 regression, not a linux one
--HG--
rename : tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini => tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/30.eon/ref/alpha/linux/o3-timing/config.out => tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out
rename : tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt
rename : tests/long/30.eon/ref/alpha/linux/o3-timing/stderr => tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr
rename : tests/long/30.eon/ref/alpha/linux/o3-timing/stdout => tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout
rename : tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini => tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out => tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out
rename : tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt
rename : tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr => tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr
rename : tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout => tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout
rename : tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini => tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/30.eon/ref/alpha/linux/simple-timing/config.out => tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out
rename : tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt
rename : tests/long/30.eon/ref/alpha/linux/simple-timing/stderr => tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr
rename : tests/long/30.eon/ref/alpha/linux/simple-timing/stdout => tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout
extra : convert_revision : 1d811462a3b90e8041b8f5da1cad9290646dbacc
Diffstat (limited to 'tests/long/30.eon/ref/alpha/tru64/simple-timing')
5 files changed, 680 insertions, 0 deletions
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini new file mode 100644 index 000000000..452538e49 --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -0,0 +1,213 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload +clock=1 +cpu_id=0 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +system=system +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing +egid=100 +env= +euid=100 +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out new file mode 100644 index 000000000..602da9705 --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out @@ -0,0 +1,201 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 +zero=false + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.workload] +type=LiveProcess +cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon +input=cin +output=cout +env= +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[statsreset] +reset_cycle=0 + diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt new file mode 100644 index 000000000..328856ce7 --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt @@ -0,0 +1,216 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 689508 # Simulator instruction rate (inst/s) +host_mem_usage 185012 # Number of bytes of host memory used +host_seconds 578.19 # Real time elapsed on the host +host_tick_rate 1033135 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 398664450 # Number of instructions simulated +sim_seconds 0.000597 # Number of seconds simulated +sim_ticks 597346012 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 94754482 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3956.610526 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2956.610526 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 94753532 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3758780 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2808780 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3940.471580 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2940.471580 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73517525 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 12617390 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 9415390 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 40527.711224 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 168275209 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3944.164258 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency +system.cpu.dcache.demand_hits 168271057 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 16376170 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 12224170 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 168275209 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3944.164258 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 168271057 # number of overall hits +system.cpu.dcache.overall_miss_latency 16376170 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_misses 4152 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 12224170 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 764 # number of replacements +system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 3222.413784 # Cycle average of tags in use +system.cpu.dcache.total_refs 168271057 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 625 # number of writebacks +system.cpu.icache.ReadReq_accesses 398664451 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3820.906097 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2820.906097 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 398660777 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 14038009 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 3674 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 10364009 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 3674 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 108508.649156 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 398664451 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3820.906097 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency +system.cpu.icache.demand_hits 398660777 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 14038009 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses +system.cpu.icache.demand_misses 3674 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10364009 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 3674 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 398664451 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3820.906097 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 398660777 # number of overall hits +system.cpu.icache.overall_miss_latency 14038009 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses +system.cpu.icache.overall_misses 3674 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10364009 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 3674 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 1770 # number of replacements +system.cpu.icache.sampled_refs 3674 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 1765.882838 # Cycle average of tags in use +system.cpu.icache.total_refs 398660777 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 7826 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2983.265505 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1924.984530 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 21404930 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.916816 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 7175 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 13811764 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916816 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 7175 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.177840 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 7826 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2983.265505 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 21404930 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.916816 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7175 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 13811764 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.916816 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7175 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 8451 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2983.265505 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 1276 # number of overall hits +system.cpu.l2cache.overall_miss_latency 21404930 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.849012 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7175 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 13811764 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.849012 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7175 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 7175 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 6344.042673 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 597346012 # number of cpu cycles simulated +system.cpu.num_insts 398664450 # Number of instructions executed +system.cpu.num_refs 174183390 # Number of memory references +system.cpu.workload.PROG:num_syscalls 215 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr new file mode 100644 index 000000000..8534c55aa --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr @@ -0,0 +1,48 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... +getting pixel output filename pixels_out.cook +opening control file chair.control.cook +opening camera file chair.camera +opening surfaces file chair.surfaces +reading data +processing 8parts +Grid measure is 6 by 3.0001 by 6 +cell dimension is 0.863065 +Creating grid for list of length 21 +Grid size = 7 by 4 by 7 +Total occupancy = 236 +reading control stream +reading camera stream +Writing to chair.cook.ppm +calculating 15 by 15 image with 196 samples +col 0. . . +col 1. . . +col 2. . . +col 3. . . +col 4. . . +col 5. . . +col 6. . . +col 7. . . +col 8. . . +col 9. . . +col 10. . . +col 11. . . +col 12. . . +col 13. . . +col 14. . . +Writing to chair.cook.ppm +0 8 14 +1 8 14 +2 8 14 +3 8 14 +4 8 14 +5 8 14 +6 8 14 +7 8 14 +8 8 14 +9 8 14 +10 8 14 +11 8 14 +12 8 14 +13 8 14 +14 8 14 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout new file mode 100644 index 000000000..039e2d4ce --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout @@ -0,0 +1,2 @@ +Eon, Version 1.1 +OO-style eon Time= 0.000000 |