diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2011-09-13 12:58:09 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2011-09-13 12:58:09 -0400 |
| commit | 28a2236ec18e3d5a82d6f7caffbf8285aec48b38 (patch) | |
| tree | bfd2d8d78733f95b30e9f671229ce2f0f55f4d94 /tests/long/30.eon/ref/alpha | |
| parent | 649c239ceef2d107fae253b1008c6f214f242d73 (diff) | |
| download | gem5-28a2236ec18e3d5a82d6f7caffbf8285aec48b38.tar.xz | |
O3: Update stats for new ordering fix.
Diffstat (limited to 'tests/long/30.eon/ref/alpha')
| -rw-r--r-- | tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini | 2 | ||||
| -rwxr-xr-x | tests/long/30.eon/ref/alpha/tru64/o3-timing/simout | 8 | ||||
| -rw-r--r-- | tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 746 |
3 files changed, 378 insertions, 378 deletions
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 9f597bc96..01d03e5c5 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/eon +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index cbdf9cdc6..46133d214 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 14:47:20 -gem5 started Aug 17 2011 15:37:38 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 16:10:02 +gem5 started Aug 20 2011 16:10:09 +gem5 executing on zizzer command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -13,4 +13,4 @@ info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.083333 -Exiting @ tick 90005685500 because target called exit() +Exiting @ tick 89480174500 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 17e0eeb5a..f27e3deec 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.090006 # Number of seconds simulated -sim_ticks 90005685500 # Number of ticks simulated +sim_seconds 0.089480 # Number of seconds simulated +sim_ticks 89480174500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147306 # Simulator instruction rate (inst/s) -host_tick_rate 35301564 # Simulator tick rate (ticks/s) -host_mem_usage 258568 # Number of bytes of host memory used -host_seconds 2549.62 # Real time elapsed on the host +host_inst_rate 168732 # Simulator instruction rate (inst/s) +host_tick_rate 40200085 # Simulator tick rate (ticks/s) +host_mem_usage 211620 # Number of bytes of host memory used +host_seconds 2225.87 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 105557144 # DTB read hits -system.cpu.dtb.read_misses 98530 # DTB read misses +system.cpu.dtb.read_hits 105444914 # DTB read hits +system.cpu.dtb.read_misses 94699 # DTB read misses system.cpu.dtb.read_acv 48617 # DTB read access violations -system.cpu.dtb.read_accesses 105655674 # DTB read accesses -system.cpu.dtb.write_hits 79803143 # DTB write hits -system.cpu.dtb.write_misses 1575 # DTB write misses +system.cpu.dtb.read_accesses 105539613 # DTB read accesses +system.cpu.dtb.write_hits 79763652 # DTB write hits +system.cpu.dtb.write_misses 1536 # DTB write misses system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 79804718 # DTB write accesses -system.cpu.dtb.data_hits 185360287 # DTB hits -system.cpu.dtb.data_misses 100105 # DTB misses +system.cpu.dtb.write_accesses 79765188 # DTB write accesses +system.cpu.dtb.data_hits 185208566 # DTB hits +system.cpu.dtb.data_misses 96235 # DTB misses system.cpu.dtb.data_acv 48618 # DTB access violations -system.cpu.dtb.data_accesses 185460392 # DTB accesses -system.cpu.itb.fetch_hits 58034543 # ITB hits -system.cpu.itb.fetch_misses 355 # ITB misses +system.cpu.dtb.data_accesses 185304801 # DTB accesses +system.cpu.itb.fetch_hits 57904086 # ITB hits +system.cpu.itb.fetch_misses 346 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 58034898 # ITB accesses +system.cpu.itb.fetch_accesses 57904432 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 180011373 # number of cpu cycles simulated +system.cpu.numCycles 178960351 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 56898591 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 33211966 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3574908 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 40524300 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 31971911 # Number of BTB hits +system.cpu.BPredUnit.lookups 56765606 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 33143039 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3552012 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 40427205 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 32022628 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 10712923 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1454 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 60019462 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 503879026 # Number of instructions fetch has processed -system.cpu.fetch.Branches 56898591 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42684834 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 93650208 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12840667 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 16998273 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7695 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 58034543 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1110351 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 179889864 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.801042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.244247 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 10686505 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1330 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 59866357 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 502938652 # Number of instructions fetch has processed +system.cpu.fetch.Branches 56765606 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42709133 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 93526616 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12701088 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 16326839 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7643 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 57904086 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1110763 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 178838548 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.812250 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.245901 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 86239656 47.94% 47.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7968101 4.43% 52.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9837104 5.47% 57.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6455150 3.59% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13616411 7.57% 69.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9477434 5.27% 74.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5920004 3.29% 77.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3509603 1.95% 79.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36866401 20.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 85311932 47.70% 47.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8035871 4.49% 52.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9868460 5.52% 57.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6372149 3.56% 61.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13508487 7.55% 68.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9517347 5.32% 74.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5905302 3.30% 77.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3555081 1.99% 79.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36763919 20.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 179889864 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316083 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.799151 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 66046381 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13163939 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 87675814 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3794037 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9209693 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 10269415 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4478 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 492179347 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12338 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9209693 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 70508732 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4469526 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 393246 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 86965796 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8342871 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 478964918 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 37494 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 6850524 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 311020883 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 627865578 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 331628214 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 296237364 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 178838548 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317197 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.810336 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 65738845 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 12641259 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 87702735 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3649079 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9106630 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 10252982 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4580 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 491283130 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12139 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9106630 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 70077435 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4396073 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 392991 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 87026850 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 7838569 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 478183111 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 34338 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 6474620 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 310467420 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 626927534 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 331115388 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 295812146 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 51488564 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38437 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 301 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 23116949 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 110811715 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 85594435 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 10526782 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6196399 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 433477285 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 262 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 418941176 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1867414 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 56505676 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 32298658 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 179889864 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.328876 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.003011 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 50935101 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38371 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 296 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 21811876 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 110641644 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 85552281 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8662202 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5906832 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 433013718 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 258 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 418626838 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2003473 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 56038444 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 32198216 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 178838548 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.340809 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.008173 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 44759242 24.88% 24.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 29396949 16.34% 41.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 28140071 15.64% 56.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 26088939 14.50% 71.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 22436504 12.47% 83.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15753855 8.76% 92.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8086358 4.50% 97.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3859739 2.15% 99.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1368207 0.76% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 44336411 24.79% 24.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 29007268 16.22% 41.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 27775406 15.53% 56.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 26238037 14.67% 71.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 22251353 12.44% 83.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15664112 8.76% 92.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8263195 4.62% 97.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3972623 2.22% 99.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1330143 0.74% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 179889864 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 178838548 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 136828 1.12% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 42966 0.35% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 1217 0.01% 1.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 10365 0.09% 1.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1870140 15.36% 16.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1752756 14.40% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5345662 43.91% 75.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3013374 24.75% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 135690 1.14% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 41926 0.35% 1.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 2442 0.02% 1.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 8992 0.08% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1877041 15.76% 17.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1762283 14.79% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5120089 42.98% 75.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2964035 24.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 164274346 39.21% 39.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126487 0.51% 39.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33733978 8.05% 47.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7896269 1.88% 49.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2902886 0.69% 50.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16725004 3.99% 54.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1576072 0.38% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 108193841 25.83% 80.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 81478712 19.45% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 164031789 39.18% 39.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126165 0.51% 39.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33716465 8.05% 47.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7893369 1.89% 49.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2899949 0.69% 50.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16711518 3.99% 54.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1573138 0.38% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 108174365 25.84% 80.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 81466499 19.46% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 418941176 # Type of FU issued -system.cpu.iq.rate 2.327304 # Inst issue rate -system.cpu.iq.fu_busy_cnt 12173308 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029057 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 682905692 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 289620140 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 241865929 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 348907246 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 200439541 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 164655906 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 252869699 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 178211204 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 14135279 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 418626838 # Type of FU issued +system.cpu.iq.rate 2.339216 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11912498 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028456 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 681277012 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 289109429 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 241633599 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 348731183 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 199993522 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 164553982 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 252486483 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 178019272 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13980098 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 16057229 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 148927 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 77022 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12073707 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 15887158 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 143607 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 50570 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12031553 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 215342 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 233419 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9209693 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2342336 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 345962 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 459173536 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2310367 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 110811715 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 85594435 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 262 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 272 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 9106630 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2382208 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 372749 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 458676643 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2278358 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 110641644 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 85552281 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 258 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 129 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 14 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 77022 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3457252 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 554336 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4011588 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 410317513 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 105704327 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 8623663 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 50570 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3441219 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 544657 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3985876 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 409944817 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 105588265 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 8682021 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 25695989 # number of nop insts executed -system.cpu.iew.exec_refs 185509104 # number of memory reference insts executed -system.cpu.iew.exec_branches 48173918 # Number of branches executed -system.cpu.iew.exec_stores 79804777 # Number of stores executed -system.cpu.iew.exec_rate 2.279398 # Inst execution rate -system.cpu.iew.wb_sent 407775826 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 406521835 # cumulative count of insts written-back -system.cpu.iew.wb_producers 197958297 # num instructions producing a value -system.cpu.iew.wb_consumers 277706216 # num instructions consuming a value +system.cpu.iew.exec_nop 25662667 # number of nop insts executed +system.cpu.iew.exec_refs 185353481 # number of memory reference insts executed +system.cpu.iew.exec_branches 48120403 # Number of branches executed +system.cpu.iew.exec_stores 79765216 # Number of stores executed +system.cpu.iew.exec_rate 2.290702 # Inst execution rate +system.cpu.iew.wb_sent 407421919 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 406187581 # cumulative count of insts written-back +system.cpu.iew.wb_producers 197894075 # num instructions producing a value +system.cpu.iew.wb_consumers 277422150 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.258312 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.712834 # average fanout of values written-back +system.cpu.iew.wb_rate 2.269707 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.713332 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 398664569 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 60526277 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 60016815 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3570557 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 170680171 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.335740 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.860101 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3547729 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 169731918 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.348790 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.858024 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 71080695 41.65% 41.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 25597473 15.00% 56.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15025586 8.80% 65.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12350485 7.24% 72.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8728325 5.11% 77.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 6123095 3.59% 81.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5311766 3.11% 84.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3136870 1.84% 86.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23325876 13.67% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 70140218 41.32% 41.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 25651558 15.11% 56.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14667534 8.64% 65.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12267165 7.23% 72.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 9098146 5.36% 77.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6161287 3.63% 81.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5543706 3.27% 84.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3203239 1.89% 86.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22999065 13.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 170680171 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 169731918 # Number of insts commited each cycle system.cpu.commit.count 398664569 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 168275214 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 44587530 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365825 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 23325876 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22999065 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 606542164 # The number of ROB reads -system.cpu.rob.rob_writes 927610224 # The number of ROB writes -system.cpu.timesIdled 2703 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 121509 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 605411260 # The number of ROB reads +system.cpu.rob.rob_writes 926487800 # The number of ROB writes +system.cpu.timesIdled 2712 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 121803 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574794 # Number of Instructions Simulated system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated -system.cpu.cpi 0.479296 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.479296 # CPI: Total CPI of All Threads -system.cpu.ipc 2.086395 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.086395 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 410036032 # number of integer regfile reads -system.cpu.int_regfile_writes 175891320 # number of integer regfile writes -system.cpu.fp_regfile_reads 159397664 # number of floating regfile reads -system.cpu.fp_regfile_writes 105955330 # number of floating regfile writes +system.cpu.cpi 0.476497 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.476497 # CPI: Total CPI of All Threads +system.cpu.ipc 2.098648 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.098648 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 409675274 # number of integer regfile reads +system.cpu.int_regfile_writes 175727060 # number of integer regfile writes +system.cpu.fp_regfile_reads 159328411 # number of floating regfile reads +system.cpu.fp_regfile_writes 105866122 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2104 # number of replacements -system.cpu.icache.tagsinuse 1835.532395 # Cycle average of tags in use -system.cpu.icache.total_refs 58029268 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4030 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14399.322084 # Average number of references to valid blocks. +system.cpu.icache.replacements 2110 # number of replacements +system.cpu.icache.tagsinuse 1834.326922 # Cycle average of tags in use +system.cpu.icache.total_refs 57898804 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4037 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 14342.037156 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1835.532395 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.896256 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 58029268 # number of ReadReq hits -system.cpu.icache.demand_hits 58029268 # number of demand (read+write) hits -system.cpu.icache.overall_hits 58029268 # number of overall hits -system.cpu.icache.ReadReq_misses 5275 # number of ReadReq misses -system.cpu.icache.demand_misses 5275 # number of demand (read+write) misses -system.cpu.icache.overall_misses 5275 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 167800500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 167800500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 167800500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 58034543 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 58034543 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 58034543 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 1834.326922 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.895667 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 57898804 # number of ReadReq hits +system.cpu.icache.demand_hits 57898804 # number of demand (read+write) hits +system.cpu.icache.overall_hits 57898804 # number of overall hits +system.cpu.icache.ReadReq_misses 5282 # number of ReadReq misses +system.cpu.icache.demand_misses 5282 # number of demand (read+write) misses +system.cpu.icache.overall_misses 5282 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 167914000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 167914000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 167914000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 57904086 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 57904086 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 57904086 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000091 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000091 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000091 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 31810.521327 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 31810.521327 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 31810.521327 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 31789.852329 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 31789.852329 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 31789.852329 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -346,158 +346,158 @@ system.cpu.icache.writebacks 0 # nu system.cpu.icache.ReadReq_mshr_hits 1245 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits 1245 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits 1245 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 4030 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 4030 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 4030 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_misses 4037 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 4037 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 4037 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 123364000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 123364000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 123364000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 123459000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 123459000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 123459000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000069 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000069 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000069 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 30611.414392 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 30611.414392 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 30611.414392 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000070 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000070 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000070 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 30581.867724 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 30581.867724 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 30581.867724 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 783 # number of replacements -system.cpu.dcache.tagsinuse 3295.270928 # Cycle average of tags in use -system.cpu.dcache.total_refs 164706127 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 39384.535390 # Average number of references to valid blocks. +system.cpu.dcache.replacements 793 # number of replacements +system.cpu.dcache.tagsinuse 3296.196945 # Cycle average of tags in use +system.cpu.dcache.total_refs 164730953 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4193 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 39287.134033 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3295.270928 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.804510 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 91204849 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 73501271 # number of WriteReq hits +system.cpu.dcache.occ_blocks::0 3296.196945 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.804736 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 91229707 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 73501239 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 164706120 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 164706120 # number of overall hits -system.cpu.dcache.ReadReq_misses 1662 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 19457 # number of WriteReq misses -system.cpu.dcache.demand_misses 21119 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 21119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 55598500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 568882000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 624480500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 624480500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 91206511 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits 164730946 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 164730946 # number of overall hits +system.cpu.dcache.ReadReq_misses 1678 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 19489 # number of WriteReq misses +system.cpu.dcache.demand_misses 21167 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 21167 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 55919500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 568883000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 624802500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 624802500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 91231385 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 73520728 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 164727239 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 164727239 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses 164752113 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 164752113 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000265 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate 0.000128 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.000128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33452.767750 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 29237.909236 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 29569.605568 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 29569.605568 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency 33325.089392 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 29189.953307 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 29517.763500 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 29517.763500 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3875 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2600 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 661 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 671 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 16266 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 16937 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 16937 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 991 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 3191 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 4182 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 4182 # number of overall MSHR misses +system.cpu.dcache.writebacks 671 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 680 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 16294 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 16974 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 16974 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 998 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 3195 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 4193 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 4193 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 31558000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 113135500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 144693500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 144693500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 31703500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 113133500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 144837000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 144837000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31844.601413 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35454.559699 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34599.115256 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34599.115256 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31767.034068 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35409.546166 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34542.570952 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34542.570952 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 9 # number of replacements -system.cpu.l2cache.tagsinuse 4001.784111 # Cycle average of tags in use -system.cpu.l2cache.total_refs 795 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4839 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.164290 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 10 # number of replacements +system.cpu.l2cache.tagsinuse 4007.455925 # Cycle average of tags in use +system.cpu.l2cache.total_refs 810 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4847 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.167114 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3624.039188 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 377.744922 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.110597 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011528 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 722 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 661 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 782 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 782 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4299 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 3131 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7430 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7430 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 147966000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 108412500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 256378500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 256378500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 661 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 3191 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8212 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8212 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.856204 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.981197 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.904774 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.904774 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34418.702024 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34625.519004 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34505.854643 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34505.854643 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 3000 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 3629.785283 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 377.670641 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.110772 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.011526 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 730 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 671 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 65 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 795 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 795 # number of overall hits +system.cpu.l2cache.ReadReq_misses 4305 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 3130 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 7435 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 7435 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 148163500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 108392000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 256555500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 256555500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 5035 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 671 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 3195 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 8230 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 8230 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.855015 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.979656 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.903402 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.903402 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34416.608595 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34630.031949 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34506.455952 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34506.455952 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4299 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 3131 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 7430 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 7430 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 4305 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 3130 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 7435 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 7435 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 134126000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 98548000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 232674000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 232674000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 134314000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 98534000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 232848000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 232848000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.856204 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981197 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.904774 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.904774 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31199.348686 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31474.928138 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31315.477793 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31315.477793 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.855015 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.979656 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.903402 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.903402 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31199.535424 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31480.511182 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31317.821116 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31317.821116 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |