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authorAli Saidi <saidi@eecs.umich.edu>2007-08-12 19:43:55 -0400
committerAli Saidi <saidi@eecs.umich.edu>2007-08-12 19:43:55 -0400
commitd114e5fae6ffb83a1145208532def7654cc9dd75 (patch)
treed54b53635428baefbb0ef25715e1059a2bad1185 /tests/long/30.eon/ref/alpha
parent02353a60ee6ce831302067aae38bc31b739f14e5 (diff)
downloadgem5-d114e5fae6ffb83a1145208532def7654cc9dd75.tar.xz
Regression: Update stats for cache changes.
--HG-- extra : convert_revision : 005672e722dec00cb4c38501b5189b4eb7515ca1
Diffstat (limited to 'tests/long/30.eon/ref/alpha')
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini72
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt593
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout2
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini38
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt181
5 files changed, 468 insertions, 418 deletions
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
index af33f850b..24e6c40a6 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
+children=dcache fuPool icache l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -21,6 +21,7 @@ SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+cachePorts=200
choiceCtrBits=2
choicePredictorSize=8192
clock=500
@@ -74,8 +75,18 @@ renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
squashWidth=8
system=system
+tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
@@ -85,21 +96,21 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -107,12 +118,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=262144
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@@ -128,11 +137,11 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu.fuPool.FUList0]
type=FUDesc
-children=opList0
+children=opList
count=6
-opList=system.cpu.fuPool.FUList0.opList0
+opList=system.cpu.fuPool.FUList0.opList
-[system.cpu.fuPool.FUList0.opList0]
+[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
@@ -206,11 +215,11 @@ opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList0
+children=opList
count=0
-opList=system.cpu.fuPool.FUList4.opList0
+opList=system.cpu.fuPool.FUList4.opList
-[system.cpu.fuPool.FUList4.opList0]
+[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
@@ -218,11 +227,11 @@ opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
-children=opList0
+children=opList
count=0
-opList=system.cpu.fuPool.FUList5.opList0
+opList=system.cpu.fuPool.FUList5.opList
-[system.cpu.fuPool.FUList5.opList0]
+[system.cpu.fuPool.FUList5.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
@@ -248,11 +257,11 @@ opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
-children=opList0
+children=opList
count=1
-opList=system.cpu.fuPool.FUList7.opList0
+opList=system.cpu.fuPool.FUList7.opList
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList7.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
@@ -260,21 +269,21 @@ opLat=3
[system.cpu.icache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -282,12 +291,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=131072
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@@ -298,21 +305,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -320,12 +327,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=2097152
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -343,6 +348,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
@@ -366,7 +374,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt
index f3f9842a2..ce15a47de 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -1,112 +1,114 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 36408912 # Number of BTB hits
-global.BPredUnit.BTBLookups 43706931 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 1105 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 5391565 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 33884568 # Number of conditional branches predicted
-global.BPredUnit.lookups 59377619 # Number of BP lookups
-global.BPredUnit.usedRAS 11768977 # Number of times the RAS was used to get a target.
-host_inst_rate 72337 # Simulator instruction rate (inst/s)
-host_mem_usage 157124 # Number of bytes of host memory used
-host_seconds 5192.02 # Real time elapsed on the host
-host_tick_rate 28301038 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 55015552 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 43012918 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 120933927 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 90962569 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 38073438 # Number of BTB hits
+global.BPredUnit.BTBLookups 45542237 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 1066 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 5897861 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 35152227 # Number of conditional branches predicted
+global.BPredUnit.lookups 62262084 # Number of BP lookups
+global.BPredUnit.usedRAS 12565322 # Number of times the RAS was used to get a target.
+host_inst_rate 169929 # Simulator instruction rate (inst/s)
+host_mem_usage 207944 # Number of bytes of host memory used
+host_seconds 2210.19 # Real time elapsed on the host
+host_tick_rate 59827386 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 71764383 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 51661369 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 124318593 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 91863744 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 375574819 # Number of instructions simulated
-sim_seconds 0.146939 # Number of seconds simulated
-sim_ticks 146939447000 # Number of ticks simulated
-system.cpu.commit.COM:branches 44587532 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 12019969 # number cycles where commit BW limit reached
+sim_insts 375574833 # Number of instructions simulated
+sim_seconds 0.132230 # Number of seconds simulated
+sim_ticks 132229900500 # Number of ticks simulated
+system.cpu.commit.COM:branches 44587535 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 12177812 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 280687503
+system.cpu.commit.COM:committed_per_cycle.samples 249309209
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 153383398 5464.56%
- 1 43042738 1533.48%
- 2 19983570 711.95%
- 3 20747693 739.17%
- 4 12078292 430.31%
- 5 11042042 393.39%
- 6 5000100 178.14%
- 7 3389701 120.76%
- 8 12019969 428.23%
+ 0 114305349 4584.88%
+ 1 51380693 2060.92%
+ 2 21363734 856.92%
+ 3 20883024 837.64%
+ 4 12699516 509.39%
+ 5 8486510 340.40%
+ 6 4833732 193.89%
+ 7 3178839 127.51%
+ 8 12177812 488.46%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
-system.cpu.commit.COM:count 398664594 # Number of instructions committed
-system.cpu.commit.COM:loads 100651995 # Number of loads committed
+system.cpu.commit.COM:count 398664608 # Number of instructions committed
+system.cpu.commit.COM:loads 100651996 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 174183397 # Number of memory references committed
+system.cpu.commit.COM:refs 174183399 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 5387368 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions
+system.cpu.commit.branchMispredicts 5893662 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 398664608 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 80492961 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 375574819 # Number of Instructions Simulated
-system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated
-system.cpu.cpi 0.782478 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.782478 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 96341397 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 5402.232747 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4689.672802 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 96339919 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 7984500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1478 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 4586500 # number of ReadReq MSHR miss cycles
+system.cpu.commit.commitSquashedInsts 93436434 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 375574833 # Number of Instructions Simulated
+system.cpu.committedInsts_total 375574833 # Number of Instructions Simulated
+system.cpu.cpi 0.704145 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.704145 # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses 96516428 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 11350.662589 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5775.739042 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 96515447 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 11135000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 981 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 512 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 5666000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 978 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 5858.789942 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4984.052533 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 73511622 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 53356000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000124 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 9107 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 5909 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 15939000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 3198 # number of WriteReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses 981 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 73513288 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 23676.737160 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6083.836858 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 73509978 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 78370000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 3310 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 7442 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 20137500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 3310 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 40673.261734 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 40714.928400 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 169862126 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 5795.040151 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 4915.110153 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 169851541 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 61340500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000062 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 10585 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 6409 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 20525500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_accesses 170029716 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 20858.774179 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 6013.400140 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 170025425 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 89505000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 4291 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 7954 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 25803500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 4176 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 4291 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 169862126 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 5795.040151 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 4915.110153 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 170029716 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 20858.774179 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 6013.400140 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 169851541 # number of overall hits
-system.cpu.dcache.overall_miss_latency 61340500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000062 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 10585 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 6409 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 20525500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_hits 170025425 # number of overall hits
+system.cpu.dcache.overall_miss_latency 89505000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 4291 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 7954 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 25803500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 4176 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses 4291 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -118,92 +120,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 781 # number of replacements
+system.cpu.dcache.replacements 780 # number of replacements
system.cpu.dcache.sampled_refs 4176 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3294.483088 # Cycle average of tags in use
-system.cpu.dcache.total_refs 169851541 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 3294.806600 # Cycle average of tags in use
+system.cpu.dcache.total_refs 170025541 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 637 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 7091571 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 4262 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 10528111 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 508290393 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 182764130 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 90473414 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 13191511 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 12840 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 358389 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 59377619 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 61063139 # Number of cache lines fetched
-system.cpu.fetch.Cycles 154416855 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 2298760 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 522129068 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 5723447 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.202048 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 61063139 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 48177889 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.776680 # Number of inst fetches per cycle
+system.cpu.dcache.writebacks 635 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 14093330 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 4329 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 11426166 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 530907169 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 132358480 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 102072460 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 15149848 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 12784 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 784940 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 62262084 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 64149519 # Number of cache lines fetched
+system.cpu.fetch.Cycles 169628877 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 1267942 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 544672632 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 6256256 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.235432 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 64149519 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 50638760 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 2.059573 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 293879015
+system.cpu.fetch.rateDist.samples 264459058
system.cpu.fetch.rateDist.min_value 0
- 0 200525300 6823.40%
- 1 7846897 267.01%
- 2 7291722 248.12%
- 3 6200462 210.99%
- 4 13845529 471.13%
- 5 7438768 253.12%
- 6 7492914 254.97%
- 7 2335483 79.47%
- 8 40901940 1391.80%
+ 0 158979701 6011.51%
+ 1 11898103 449.90%
+ 2 12511338 473.09%
+ 3 6558243 247.99%
+ 4 15951093 603.16%
+ 5 8933216 337.79%
+ 6 6667977 252.14%
+ 7 4076286 154.14%
+ 8 38883101 1470.29%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 61063139 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 5151.654640 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 4230.492813 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 61059120 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 20704500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000066 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 4019 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 16482000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 64149331 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 7193.164363 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 5001.152074 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 64145425 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 28096500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 3906 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 188 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 19534500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 3906 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 15672.258727 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 16422.279826 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 61063139 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 5151.654640 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 4230.492813 # average overall mshr miss latency
-system.cpu.icache.demand_hits 61059120 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 20704500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000066 # miss rate for demand accesses
-system.cpu.icache.demand_misses 4019 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 123 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 16482000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 64149331 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 7193.164363 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 5001.152074 # average overall mshr miss latency
+system.cpu.icache.demand_hits 64145425 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 28096500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses
+system.cpu.icache.demand_misses 3906 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 188 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 19534500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 3906 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 61063139 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 5151.654640 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 4230.492813 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 64149331 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 7193.164363 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 5001.152074 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 61059120 # number of overall hits
-system.cpu.icache.overall_miss_latency 20704500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000066 # miss rate for overall accesses
-system.cpu.icache.overall_misses 4019 # number of overall misses
-system.cpu.icache.overall_mshr_hits 123 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 16482000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses
+system.cpu.icache.overall_hits 64145425 # number of overall hits
+system.cpu.icache.overall_miss_latency 28096500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses
+system.cpu.icache.overall_misses 3906 # number of overall misses
+system.cpu.icache.overall_mshr_hits 188 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 19534500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 3906 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -215,162 +217,183 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 1976 # number of replacements
-system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 1984 # number of replacements
+system.cpu.icache.sampled_refs 3906 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1822.947356 # Cycle average of tags in use
-system.cpu.icache.total_refs 61059120 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1827.150129 # Cycle average of tags in use
+system.cpu.icache.total_refs 64145425 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 6367 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 50329288 # Number of branches executed
-system.cpu.iew.EXEC:nop 26718868 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.409679 # Inst execution rate
-system.cpu.iew.EXEC:refs 190324589 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 79889528 # Number of stores executed
+system.cpu.idleCycles 557628 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 51104102 # Number of branches executed
+system.cpu.iew.EXEC:nop 27319155 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.584545 # Inst execution rate
+system.cpu.iew.EXEC:refs 191326029 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 79588041 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 266244037 # num instructions consuming a value
-system.cpu.iew.WB:count 411128901 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.717332 # average fanout of values written-back
+system.cpu.iew.WB:consumers 282498519 # num instructions consuming a value
+system.cpu.iew.WB:count 414521159 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.706139 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 190985280 # num instructions producing a value
-system.cpu.iew.WB:rate 1.398973 # insts written-back per cycle
-system.cpu.iew.WB:sent 411485990 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 6032644 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 1137801 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 120933927 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 222 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 6771454 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 90962569 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 479157588 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 110435061 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 10298797 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 414275208 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 67 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 199483248 # num instructions producing a value
+system.cpu.iew.WB:rate 1.567430 # insts written-back per cycle
+system.cpu.iew.WB:sent 415435713 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 6236762 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 2781988 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 124318593 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 240 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 6814163 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 91863744 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 492099709 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 111737988 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 8739319 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 419047233 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 168412 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 21083 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 13191511 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 115109 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 50946 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 15149848 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 506738 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 7097511 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 3223 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads 8219638 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 31016 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 404889 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 176320 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 20281932 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 17431167 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 404889 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 802823 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 5229821 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.277991 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.277991 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 424574005 # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 502753 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 178119 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 23666597 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 18332341 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 502753 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 955669 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 5281093 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.420162 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.420162 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 427786552 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 33581 0.01% # Type of FU issued
- IntAlu 163144501 38.43% # Type of FU issued
- IntMult 2125088 0.50% # Type of FU issued
+ No_OpClass 33581 0.01% # Type of FU issued
+ IntAlu 166519693 38.93% # Type of FU issued
+ IntMult 2147905 0.50% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 34659405 8.16% # Type of FU issued
- FloatCmp 7790033 1.83% # Type of FU issued
- FloatCvt 2881594 0.68% # Type of FU issued
- FloatMult 16618307 3.91% # Type of FU issued
- FloatDiv 1566111 0.37% # Type of FU issued
+ FloatAdd 35254026 8.24% # Type of FU issued
+ FloatCmp 7817685 1.83% # Type of FU issued
+ FloatCvt 2969947 0.69% # Type of FU issued
+ FloatMult 16787400 3.92% # Type of FU issued
+ FloatDiv 1570522 0.37% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 113765764 26.80% # Type of FU issued
- MemWrite 81989621 19.31% # Type of FU issued
+ MemRead 113248293 26.47% # Type of FU issued
+ MemWrite 81437500 19.04% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 9576176 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.022555 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 9448608 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.022087 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 12415 0.13% # attempts to use FU when none available
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 17181 0.18% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 46832 0.49% # attempts to use FU when none available
- FloatCmp 11338 0.12% # attempts to use FU when none available
- FloatCvt 25702 0.27% # attempts to use FU when none available
- FloatMult 2984764 31.17% # attempts to use FU when none available
- FloatDiv 331535 3.46% # attempts to use FU when none available
+ FloatAdd 604 0.01% # attempts to use FU when none available
+ FloatCmp 32516 0.34% # attempts to use FU when none available
+ FloatCvt 8012 0.08% # attempts to use FU when none available
+ FloatMult 2137313 22.62% # attempts to use FU when none available
+ FloatDiv 917798 9.71% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 4942933 51.62% # attempts to use FU when none available
- MemWrite 1220657 12.75% # attempts to use FU when none available
+ MemRead 5261958 55.69% # attempts to use FU when none available
+ MemWrite 1073226 11.36% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 293879015
+system.cpu.iq.ISSUE:issued_per_cycle.samples 264459058
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 129735390 4414.59%
- 1 52072154 1771.89%
- 2 39787134 1353.86%
- 3 29621395 1007.95%
- 4 21763636 740.56%
- 5 12600620 428.77%
- 6 4911147 167.11%
- 7 2561440 87.16%
- 8 826099 28.11%
+ 0 94473273 3572.32%
+ 1 57538428 2175.70%
+ 2 41283183 1561.04%
+ 3 28951087 1094.73%
+ 4 22152944 837.67%
+ 5 11939207 451.46%
+ 6 5137200 194.25%
+ 7 2172402 82.15%
+ 8 811334 30.68%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 1.444724 # Inst issue rate
-system.cpu.iq.iqInstsAdded 452438498 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 424574005 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 222 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 75756994 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 1109878 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 55099010 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 8070 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 4677.770224 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2436.233855 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 715 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 34405000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.911400 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 7355 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 17918500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.911400 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 7355 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 637 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 637 # number of Writeback hits
+system.cpu.iq.ISSUE:rate 1.617591 # Inst issue rate
+system.cpu.iq.iqInstsAdded 464780314 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 427786552 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 240 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 88460147 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 742026 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 67499517 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadExReq_accesses 3199 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 4646.764614 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2646.764614 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 14865000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 3199 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 8467000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 3199 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 4883 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 4356.375525 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2356.375525 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 601 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 18654000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.876920 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 4282 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 10090000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.876920 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 4282 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 117 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 4482.905983 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2482.905983 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 524500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 117 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 290500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 117 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 635 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 635 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 635 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.183821 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.139496 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 8070 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 4677.770224 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2436.233855 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 715 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 34405000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.911400 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 7355 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 8082 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 4480.550729 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2480.550729 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 601 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 33519000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.925637 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 7481 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 17918500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.911400 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 7355 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 18557000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.925637 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 7481 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 8707 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 4677.770224 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2436.233855 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 8082 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 4480.550729 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2480.550729 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1352 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 34405000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.844723 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 7355 # number of overall misses
+system.cpu.l2cache.overall_hits 601 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 33519000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.925637 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 7481 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 17918500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.844723 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 7355 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 18557000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.925637 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 7481 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -382,31 +405,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 7355 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 6 # number of replacements
+system.cpu.l2cache.sampled_refs 4165 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 6644.823451 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1352 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 3521.188558 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 581 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 293879015 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 3715266 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 115195 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 185747540 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 2602652 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 654991501 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 496454048 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 320284080 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 87805227 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 13191511 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 3048084 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 60751739 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 371387 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 37057 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 7965999 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 243 # count of temporary serializing insts renamed
-system.cpu.timesIdled 133 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.numCycles 264459058 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 6942912 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 259532351 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 1128496 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 136398173 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 4996172 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 682131973 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 517993086 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 334891535 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 98637930 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 15149848 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 6975590 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 75359184 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 354605 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 37909 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 15667924 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 253 # count of temporary serializing insts renamed
+system.cpu.timesIdled 375 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout
index 50ed34325..f2cd9657b 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout
@@ -1,2 +1,2 @@
Eon, Version 1.1
-OO-style eon Time= 0.133333
+OO-style eon Time= 0.116667
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
index ca3706b7b..2f7931c5a 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
+children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@@ -24,27 +24,28 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
+tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -52,12 +53,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=262144
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -90,12 +89,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=131072
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -128,12 +125,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=2097152
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -151,6 +146,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
@@ -174,7 +172,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt
index 28c7cc183..5d80e04f0 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 579996 # Simulator instruction rate (inst/s)
-host_mem_usage 156556 # Number of bytes of host memory used
-host_seconds 687.36 # Real time elapsed on the host
-host_tick_rate 824955659 # Simulator tick rate (ticks/s)
+host_inst_rate 1477024 # Simulator instruction rate (inst/s)
+host_mem_usage 207136 # Number of bytes of host memory used
+host_seconds 269.91 # Real time elapsed on the host
+host_tick_rate 2101151515 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664611 # Number of instructions simulated
-sim_seconds 0.567040 # Number of seconds simulated
-sim_ticks 567040254000 # Number of ticks simulated
+sim_seconds 0.567124 # Number of seconds simulated
+sim_ticks 567123959000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 13741.052632 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12741.052632 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 24216.842105 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22216.842105 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 13054000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 23006000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 12104000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 21106000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 13962.523423 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12962.523423 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 73517528 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 44708000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 41506000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 73517416 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 82850000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 3314 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 76222000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 3314 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
@@ -37,31 +37,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 13911.849711 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 12911.849711 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 168271068 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 57762000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_avg_miss_latency 24825.515947 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 22825.515947 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 168270956 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 105856000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses 4264 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 53610000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 97328000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 4264 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 13911.849711 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 12911.849711 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 24825.515947 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 22825.515947 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 168271068 # number of overall hits
-system.cpu.dcache.overall_miss_latency 57762000 # number of overall miss cycles
+system.cpu.dcache.overall_hits 168270956 # number of overall hits
+system.cpu.dcache.overall_miss_latency 105856000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 4152 # number of overall misses
+system.cpu.dcache.overall_misses 4264 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 53610000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 97328000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses 4264 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 764 # number of replacements
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3289.654807 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 3289.454030 # Cycle average of tags in use
system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 625 # number of writebacks
system.cpu.icache.ReadReq_accesses 398664612 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 13745.167438 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12745.167438 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 23471.004628 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 21471.004628 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 398660939 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 50486000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 86209000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 46813000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 78863000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 398664612 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 13745.167438 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12745.167438 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 23471.004628 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 21471.004628 # average overall mshr miss latency
system.cpu.icache.demand_hits 398660939 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 50486000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 86209000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 46813000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 78863000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 398664612 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 13745.167438 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12745.167438 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 23471.004628 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 21471.004628 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 398660939 # number of overall hits
-system.cpu.icache.overall_miss_latency 50486000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 86209000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
system.cpu.icache.overall_misses 3673 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 46813000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 78863000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -138,57 +138,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 1769 # number of replacements
system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1795.458615 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1795.369888 # Cycle average of tags in use
system.cpu.icache.total_refs 398660939 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 7825 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 70444000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 3202 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 35222000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 3202 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 93262000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.916805 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 7174 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 78914000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916805 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 7174 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_hits 530 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 90046000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.885356 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 4093 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 45023000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885356 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 4093 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 112 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 2464000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1232000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 625 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 625 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.177865 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.128109 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 93262000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.916805 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 7174 # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits 530 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 160490000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.932268 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 7295 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 78914000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.916805 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 7174 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 80245000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.932268 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 7295 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 8450 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1276 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 93262000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.848994 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 7174 # number of overall misses
+system.cpu.l2cache.overall_hits 530 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 160490000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.932268 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 7295 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 78914000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.848994 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 7174 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 80245000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.932268 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 7295 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -200,15 +221,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 7174 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 6 # number of replacements
+system.cpu.l2cache.sampled_refs 3981 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 6483.455048 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 3355.056948 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 510 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 567040254000 # number of cpu cycles simulated
+system.cpu.numCycles 567123959000 # number of cpu cycles simulated
system.cpu.num_insts 398664611 # Number of instructions executed
system.cpu.num_refs 174183401 # Number of memory references
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls