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authorLisa Hsu <Lisa.Hsu@amd.com>2010-02-25 10:08:41 -0800
committerLisa Hsu <Lisa.Hsu@amd.com>2010-02-25 10:08:41 -0800
commitee20a7c0bddf1f2a1913ddb176910bdce4c13b9c (patch)
tree93b9bd8be890468c550b85eae4b467285b4d6811 /tests/long/30.eon/ref/alpha
parent7f3cd9a9fd636c1e48dcec20de3f6c14214d0ce4 (diff)
downloadgem5-ee20a7c0bddf1f2a1913ddb176910bdce4c13b9c.tar.xz
stats: update stats for the changes I pushed re: shared cache occupancy
Diffstat (limited to 'tests/long/30.eon/ref/alpha')
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini10
-rwxr-xr-xtests/long/30.eon/ref/alpha/tru64/o3-timing/simout10
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt16
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini2
-rwxr-xr-xtests/long/30.eon/ref/alpha/tru64/simple-atomic/simout8
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt8
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini8
-rwxr-xr-xtests/long/30.eon/ref/alpha/tru64/simple-timing/simout8
-rw-r--r--tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt16
9 files changed, 51 insertions, 35 deletions
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 561928f24..ef5381d49 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -109,7 +109,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -281,7 +281,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -316,7 +316,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -353,12 +353,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
+cwd=build/ALPHA_SE_MOESI_hammer/tests/fast/long/30.eon/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
index 319145d66..84704aca2 100755
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:50:56
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
+M5 compiled Feb 24 2010 23:12:54
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:18:35
+M5 executing on SC2B0619
+command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/long/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 31281b132..86e5c6d82 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 241043 # Simulator instruction rate (inst/s)
-host_mem_usage 197116 # Number of bytes of host memory used
-host_seconds 1558.12 # Real time elapsed on the host
-host_tick_rate 86640473 # Simulator tick rate (ticks/s)
+host_inst_rate 119207 # Simulator instruction rate (inst/s)
+host_mem_usage 198920 # Number of bytes of host memory used
+host_seconds 3150.62 # Real time elapsed on the host
+host_tick_rate 42847667 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 375574819 # Number of instructions simulated
sim_seconds 0.134997 # Number of seconds simulated
@@ -95,6 +95,8 @@ system.cpu.dcache.demand_mshr_misses 4293 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.804192 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 3293.970402 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 169022038 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 30545.726047 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency
@@ -201,6 +203,8 @@ system.cpu.icache.demand_mshr_misses 3896 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.890401 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1823.540410 # Average occupied blocks per context
system.cpu.icache.overall_accesses 63866189 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 32249.018798 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency
@@ -391,6 +395,10 @@ system.cpu.l2cache.demand_mshr_misses 7418 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.106709 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.011557 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 3496.652993 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 378.690415 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 8073 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34461.782017 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index 193b9744b..c17ad3a43 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -57,7 +57,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
index ff24c9828..799b8b93c 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 21 2009 16:38:39
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 16:39:12
-M5 executing on zizzer
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:33:35
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
index 2dd6bb319..79a1d3a15 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 3427488 # Simulator instruction rate (inst/s)
-host_mem_usage 203296 # Number of bytes of host memory used
-host_seconds 116.31 # Real time elapsed on the host
-host_tick_rate 1713741057 # Simulator tick rate (ticks/s)
+host_inst_rate 1825585 # Simulator instruction rate (inst/s)
+host_mem_usage 190564 # Number of bytes of host memory used
+host_seconds 218.38 # Real time elapsed on the host
+host_tick_rate 912792158 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664595 # Number of instructions simulated
sim_seconds 0.199332 # Number of seconds simulated
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
index cb9992f60..9f3658fe3 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -45,7 +45,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -80,7 +80,7 @@ hash_delay=1
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -115,7 +115,7 @@ hash_delay=1
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
@@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
index c7ba9a351..15db5ae30 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:06:21
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:20:32
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 5933cded2..f93d01d91 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2382679 # Simulator instruction rate (inst/s)
-host_mem_usage 212620 # Number of bytes of host memory used
-host_seconds 167.32 # Real time elapsed on the host
-host_tick_rate 3390857898 # Simulator tick rate (ticks/s)
+host_inst_rate 860135 # Simulator instruction rate (inst/s)
+host_mem_usage 198216 # Number of bytes of host memory used
+host_seconds 463.49 # Real time elapsed on the host
+host_tick_rate 1224083493 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664609 # Number of instructions simulated
sim_seconds 0.567352 # Number of seconds simulated
@@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 4264 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.802954 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 3288.899192 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 54847.560976 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency
@@ -119,6 +121,8 @@ system.cpu.icache.demand_mshr_misses 3673 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.876526 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1795.124700 # Average occupied blocks per context
system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
@@ -209,6 +213,10 @@ system.cpu.l2cache.demand_mshr_misses 7240 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.101996 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.011352 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 3342.203160 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 371.972955 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency