diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
| commit | d080581db1f9ee4e1e6d07d2b01c13c67908a391 (patch) | |
| tree | cc484b289fa5a30c4631f9faa1d8b456bffeebfc /tests/long/30.eon/ref/alpha | |
| parent | 7a7c4c5fca83a8d47c7e71c9c080a882ebe204a9 (diff) | |
| parent | 639cb0a42d953ee32bc7e96b0cdfa96cd40e9fc1 (diff) | |
| download | gem5-d080581db1f9ee4e1e6d07d2b01c13c67908a391.tar.xz | |
Merge ARM into the head. ARM will compile but may not actually work.
Diffstat (limited to 'tests/long/30.eon/ref/alpha')
15 files changed, 469 insertions, 475 deletions
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 50eaa3f41..253ff4370 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -104,16 +107,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -122,8 +123,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,16 +280,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -299,8 +296,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,16 +316,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -368,6 +359,7 @@ cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 @@ -376,6 +368,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -392,7 +385,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr index 4bb0d9bbe..f7b481bbe 100644..100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr @@ -1,11 +1,10 @@ -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data -warn: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout new file mode 100755 index 000000000..d243310c6 --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -0,0 +1,18 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:25:10 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py long/30.eon/alpha/tru64/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Eon, Version 1.1 +info: Increasing stack size by one page. +OO-style eon Time= 0.133333 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 3af370c7d..5e076a275 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,40 +1,36 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 37055347 # Number of BTB hits -global.BPredUnit.BTBLookups 45947414 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1096 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 5691744 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 35558640 # Number of conditional branches predicted -global.BPredUnit.lookups 62480259 # Number of BP lookups -global.BPredUnit.usedRAS 12398507 # Number of times the RAS was used to get a target. -host_inst_rate 155119 # Simulator instruction rate (inst/s) -host_mem_usage 205336 # Number of bytes of host memory used -host_seconds 2421.21 # Real time elapsed on the host -host_tick_rate 55712012 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 72769124 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 54049353 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 125306666 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 92782205 # Number of stores inserted to the mem dependence unit. +host_inst_rate 243217 # Simulator instruction rate (inst/s) +host_mem_usage 213460 # Number of bytes of host memory used +host_seconds 1544.20 # Real time elapsed on the host +host_tick_rate 87422028 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 375574819 # Number of instructions simulated -sim_seconds 0.134890 # Number of seconds simulated -sim_ticks 134890208500 # Number of ticks simulated +sim_seconds 0.134997 # Number of seconds simulated +sim_ticks 134996684500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 38296034 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 45834466 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1077 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 5781170 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 62209737 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 44587532 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 13065530 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 13163574 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 254286247 +system.cpu.commit.COM:committed_per_cycle.samples 254545672 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 123470433 4855.57% - 1 49744073 1956.22% - 2 18820215 740.12% - 3 19293865 758.75% - 4 12510791 492.00% - 5 8575068 337.22% - 6 5688152 223.69% - 7 3118120 122.62% - 8 13065530 513.81% + 0 123085209 4835.49% + 1 50466868 1982.63% + 2 18758377 736.94% + 3 19955031 783.95% + 4 11844121 465.30% + 5 8478667 333.09% + 6 5819307 228.62% + 7 2974518 116.86% + 8 13163574 517.14% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,406 +39,386 @@ system.cpu.commit.COM:loads 100651995 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 174183397 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 5687554 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 5776994 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 96777858 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 94782663 # The number of squashed insts skipped by commit system.cpu.committedInsts 375574819 # Number of Instructions Simulated system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated -system.cpu.cpi 0.718313 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.718313 # CPI: Total CPI of All Threads +system.cpu.cpi 0.718880 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.718880 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 95885180 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 15194.726166 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7312.880325 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 95884194 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 14982000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 986 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 536 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 7210500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_accesses 95501309 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33016.637478 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31966.971545 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 95499596 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 56557500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1713 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 729 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 31455500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 986 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 73513083 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32019.486405 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7598.791541 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73509773 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 105984500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 3310 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 7646 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 25152000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_misses 984 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 30310.747349 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36196.886371 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73502716 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 545987492 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000245 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 18013 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 14704 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 119775497 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3310 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 3309 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 3249.700000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40554.006943 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.avg_refs 40460.272684 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 32497 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 169398263 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 28157.937616 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7533.170391 # average overall mshr miss latency -system.cpu.dcache.demand_hits 169393967 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 120966500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_misses 4296 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 8182 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 32362500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 169022038 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 30545.726047 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency +system.cpu.dcache.demand_hits 169002312 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 602544992 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses +system.cpu.dcache.demand_misses 19726 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 15433 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 151230997 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4296 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 4293 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 169398263 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 28157.937616 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7533.170391 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 169022038 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 30545.726047 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 169393967 # number of overall hits -system.cpu.dcache.overall_miss_latency 120966500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_misses 4296 # number of overall misses -system.cpu.dcache.overall_mshr_hits 8182 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 32362500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 169002312 # number of overall hits +system.cpu.dcache.overall_miss_latency 602544992 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses +system.cpu.dcache.overall_misses 19726 # number of overall misses +system.cpu.dcache.overall_mshr_hits 15433 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 151230997 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4296 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 4293 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 781 # number of replacements +system.cpu.dcache.replacements 782 # number of replacements system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3296.858616 # Cycle average of tags in use -system.cpu.dcache.total_refs 169394087 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3293.970402 # Cycle average of tags in use +system.cpu.dcache.total_refs 169002559 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 636 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 18955564 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 4312 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 11369096 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 533723337 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 133094788 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 100949486 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 15490881 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 12729 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1286410 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 186077432 # DTB accesses -system.cpu.dtb.acv 11216 # DTB access violations -system.cpu.dtb.hits 186006805 # DTB hits -system.cpu.dtb.misses 70627 # DTB misses -system.cpu.dtb.read_accesses 104841123 # DTB read accesses -system.cpu.dtb.read_acv 11216 # DTB read access violations -system.cpu.dtb.read_hits 104772046 # DTB read hits -system.cpu.dtb.read_misses 69077 # DTB read misses -system.cpu.dtb.write_accesses 81236309 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 81234759 # DTB write hits -system.cpu.dtb.write_misses 1550 # DTB write misses -system.cpu.fetch.Branches 62480259 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 64020665 # Number of cache lines fetched -system.cpu.fetch.Cycles 168778939 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1468351 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 547045642 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 6042059 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.231597 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 64020665 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 49453854 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.027744 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 635 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 18875032 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 4277 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 11323346 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 531939828 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 132443197 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 101952317 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 15306974 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 12561 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1275127 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 185115437 # DTB accesses +system.cpu.dtb.acv 1 # DTB access violations +system.cpu.dtb.hits 185076670 # DTB hits +system.cpu.dtb.misses 38767 # DTB misses +system.cpu.dtb.read_accesses 104449499 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 104412186 # DTB read hits +system.cpu.dtb.read_misses 37313 # DTB read misses +system.cpu.dtb.write_accesses 80665938 # DTB write accesses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_hits 80664484 # DTB write hits +system.cpu.dtb.write_misses 1454 # DTB write misses +system.cpu.fetch.Branches 62209737 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 63866189 # Number of cache lines fetched +system.cpu.fetch.Cycles 169616790 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1519057 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 544903543 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 6123543 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.230412 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 63866189 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 50640538 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.018211 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 269777129 +system.cpu.fetch.rateDist.samples 269852647 system.cpu.fetch.rateDist.min_value 0 - 0 165019149 6116.87% - 1 11208105 415.46% - 2 10970042 406.63% - 3 7809028 289.46% - 4 16007682 593.37% - 5 8770390 325.10% - 6 6686429 247.85% - 7 3981315 147.58% - 8 39324989 1457.68% + 0 164102333 6081.18% + 1 12367121 458.29% + 2 12410556 459.90% + 3 6615129 245.14% + 4 15923029 590.06% + 5 8709903 322.77% + 6 6580254 243.85% + 7 4007808 148.52% + 8 39136514 1450.29% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 64020369 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9431.835687 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6021.951220 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 64016474 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 36737000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 3895 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 296 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 23455500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_accesses 63866189 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 32249.018798 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 30883.598563 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 63861348 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 156117500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 4841 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 945 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120322500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3895 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 16435.551733 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 16391.516427 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 64020369 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9431.835687 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6021.951220 # average overall mshr miss latency -system.cpu.icache.demand_hits 64016474 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 36737000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses -system.cpu.icache.demand_misses 3895 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 296 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 23455500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_accesses 63866189 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 32249.018798 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency +system.cpu.icache.demand_hits 63861348 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 156117500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses +system.cpu.icache.demand_misses 4841 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 945 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120322500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3895 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 64020369 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9431.835687 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6021.951220 # average overall mshr miss latency +system.cpu.icache.overall_accesses 63866189 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 32249.018798 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 64016474 # number of overall hits -system.cpu.icache.overall_miss_latency 36737000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses -system.cpu.icache.overall_misses 3895 # number of overall misses -system.cpu.icache.overall_mshr_hits 296 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 23455500 # number of overall MSHR miss cycles +system.cpu.icache.overall_hits 63861348 # number of overall hits +system.cpu.icache.overall_miss_latency 156117500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses +system.cpu.icache.overall_misses 4841 # number of overall misses +system.cpu.icache.overall_mshr_hits 945 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120322500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3895 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1973 # number of replacements -system.cpu.icache.sampled_refs 3895 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1975 # number of replacements +system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1826.958701 # Cycle average of tags in use -system.cpu.icache.total_refs 64016474 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1823.540410 # Cycle average of tags in use +system.cpu.icache.total_refs 63861348 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 3290 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 51062363 # Number of branches executed -system.cpu.iew.EXEC:nop 27214999 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.560789 # Inst execution rate -system.cpu.iew.EXEC:refs 192842691 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 81246989 # Number of stores executed +system.cpu.idleCycles 140725 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 50976851 # Number of branches executed +system.cpu.iew.EXEC:nop 27164335 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.553144 # Inst execution rate +system.cpu.iew.EXEC:refs 191842297 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 80676625 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 287107823 # num instructions consuming a value -system.cpu.iew.WB:count 417299912 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.702706 # average fanout of values written-back +system.cpu.iew.WB:consumers 285463485 # num instructions consuming a value +system.cpu.iew.WB:count 415481237 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.703314 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 201752289 # num instructions producing a value -system.cpu.iew.WB:rate 1.546813 # insts written-back per cycle -system.cpu.iew.WB:sent 418066212 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6311133 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2198946 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 125306666 # Number of dispatched load instructions +system.cpu.iew.WB:producers 200770520 # num instructions producing a value +system.cpu.iew.WB:rate 1.538857 # insts written-back per cycle +system.cpu.iew.WB:sent 416287464 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 6390313 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2178518 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 124841223 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 6339692 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 92782205 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 495443138 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 111595702 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10411801 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 421070304 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 127438 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 6302760 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 92324076 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 493447669 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 111165672 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10261544 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 419338652 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 25079 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 23538 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 15490881 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 491568 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 23746 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 15306974 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 341836 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 8710387 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 3327 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 8734674 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2193 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 505299 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 175942 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 24654671 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 19250803 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 505299 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 821714 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5489419 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.392150 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.392150 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 431482105 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 436213 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 176181 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 24189228 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 18792674 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 436213 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 847804 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 5542509 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.391052 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.391052 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 429600196 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 33581 0.01% # Type of FU issued - IntAlu 167002612 38.70% # Type of FU issued - IntMult 2153139 0.50% # Type of FU issued + IntAlu 166319014 38.71% # Type of FU issued + IntMult 2152935 0.50% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 34874757 8.08% # Type of FU issued - FloatCmp 7889981 1.83% # Type of FU issued - FloatCvt 2903377 0.67% # Type of FU issued - FloatMult 16803027 3.89% # Type of FU issued - FloatDiv 1591666 0.37% # Type of FU issued + FloatAdd 35077566 8.17% # Type of FU issued + FloatCmp 7830879 1.82% # Type of FU issued + FloatCvt 2898460 0.67% # Type of FU issued + FloatMult 16788316 3.91% # Type of FU issued + FloatDiv 1569716 0.37% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 114230521 26.47% # Type of FU issued - MemWrite 83999444 19.47% # Type of FU issued + MemRead 113503270 26.42% # Type of FU issued + MemWrite 83426459 19.42% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 10446664 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.024211 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 10457046 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.024341 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 32363 0.31% # attempts to use FU when none available + IntAlu 40640 0.39% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 95689 0.92% # attempts to use FU when none available - FloatCmp 7492 0.07% # attempts to use FU when none available - FloatCvt 12721 0.12% # attempts to use FU when none available - FloatMult 1683122 16.11% # attempts to use FU when none available - FloatDiv 1408746 13.49% # attempts to use FU when none available + FloatAdd 76056 0.73% # attempts to use FU when none available + FloatCmp 13381 0.13% # attempts to use FU when none available + FloatCvt 12891 0.12% # attempts to use FU when none available + FloatMult 1723474 16.48% # attempts to use FU when none available + FloatDiv 1473560 14.09% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 5941492 56.87% # attempts to use FU when none available - MemWrite 1265039 12.11% # attempts to use FU when none available + MemRead 5907144 56.49% # attempts to use FU when none available + MemWrite 1209900 11.57% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 269777129 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 99508340 3688.54% - 1 57898126 2146.15% - 2 39403533 1460.60% - 3 28850583 1069.42% - 4 24598298 911.80% - 5 10625217 393.85% - 6 6146486 227.84% - 7 2145397 79.52% - 8 601149 22.28% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.599383 # Inst issue rate -system.cpu.iq.iqInstsAdded 468227900 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 431482105 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::samples 269852647 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 99465935 36.86% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 57766030 21.41% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 39984554 14.82% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 29664959 10.99% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 23966120 8.88% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 10452563 3.87% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 5712016 2.12% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 2252970 0.83% +system.cpu.iq.ISSUE:issued_per_cycle::8 587500 0.22% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 269852647 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.591981 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.720906 +system.cpu.iq.ISSUE:rate 1.591151 # Inst issue rate +system.cpu.iq.iqInstsAdded 466283095 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 429600196 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 91553989 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1306748 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 89615992 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 918381 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 68680838 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 64020959 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 68228113 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 63866476 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 64020665 # ITB hits -system.cpu.itb.misses 294 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 3195 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 6098.591549 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3098.591549 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 19485000 # number of ReadExReq miss cycles +system.cpu.itb.hits 63866189 # ITB hits +system.cpu.itb.misses 287 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 3197 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.340006 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.625899 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 110604499 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 3195 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9900000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 3197 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 100602000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 3195 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 4877 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5592.080378 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2592.080378 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 647 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 23654500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.867336 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4230 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10964500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.867336 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4230 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 121 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5698.347107 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2698.347107 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 689500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 3197 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 4876 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34359.867330 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31168.325041 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 655 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 145033000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.865669 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4221 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 131561500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.865669 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4221 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 119 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34441.176471 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31285.714286 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 4098500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 121 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 326500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 119 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3723000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 121 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 636 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 636 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.UpgradeReq_mshr_misses 119 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 635 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 635 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs 3000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.128309 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 0.130240 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 6000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 8072 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5810.033670 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2810.033670 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 647 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 43139500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.919846 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7425 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 8073 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34461.782017 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 655 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 255637499 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.918865 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7418 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 20864500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.919846 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7425 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 232163500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.918865 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7418 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 8072 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5810.033670 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2810.033670 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 8073 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34461.782017 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 647 # number of overall hits -system.cpu.l2cache.overall_miss_latency 43139500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.919846 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7425 # number of overall misses +system.cpu.l2cache.overall_hits 655 # number of overall hits +system.cpu.l2cache.overall_miss_latency 255637499 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.918865 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7418 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 20864500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.919846 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7425 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 232163500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.918865 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7418 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 15 # number of replacements -system.cpu.l2cache.sampled_refs 4684 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 14 # number of replacements +system.cpu.l2cache.sampled_refs 4676 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3884.477480 # Cycle average of tags in use -system.cpu.l2cache.total_refs 601 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3875.343408 # Cycle average of tags in use +system.cpu.l2cache.total_refs 609 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 269780419 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 8898218 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 73961217 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 54131405 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 92324076 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 269993372 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 8452992 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1493929 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 138057394 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 7378387 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 685335905 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 519882318 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 336260549 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 96875532 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 15490881 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 10098203 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 76728208 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 356901 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 37939 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 22218757 # count of insts added to the skid buffer +system.cpu.rename.RENAME:IQFullEvents 1780176 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 137359458 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 7392558 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 684397837 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 518816398 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 335732022 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 97960614 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 15306974 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 10399659 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 76199681 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 372950 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 37950 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 22290547 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 251 # count of temporary serializing insts renamed -system.cpu.timesIdled 727 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 3086 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout deleted file mode 100644 index 50ed34325..000000000 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout +++ /dev/null @@ -1,2 +0,0 @@ -Eon, Version 1.1 -OO-style eon Time= 0.133333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini index bfc3d0e40..b219ea49a 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,13 +55,16 @@ cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -65,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -72,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr index 56a19a708..f7b481bbe 100644..100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr @@ -1,12 +1,10 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data -warn: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout new file mode 100755 index 000000000..320d9365d --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout @@ -0,0 +1,18 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:27:51 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py long/30.eon/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Eon, Version 1.1 +info: Increasing stack size by one page. +OO-style eon Time= 0.183333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index e32cacf16..f57fc8170 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2526947 # Simulator instruction rate (inst/s) -host_mem_usage 181828 # Number of bytes of host memory used -host_seconds 157.77 # Real time elapsed on the host -host_tick_rate 1263471125 # Simulator tick rate (ticks/s) +host_inst_rate 3515833 # Simulator instruction rate (inst/s) +host_mem_usage 203260 # Number of bytes of host memory used +host_seconds 113.39 # Real time elapsed on the host +host_tick_rate 1757913715 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664595 # Number of instructions simulated sim_seconds 0.199332 # Number of seconds simulated diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout deleted file mode 100644 index 5f057b8dd..000000000 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout +++ /dev/null @@ -1,2 +0,0 @@ -Eon, Version 1.1 -OO-style eon Time= 0.183333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index 6912167e0..86203bb88 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,6 +26,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -39,16 +43,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -57,8 +59,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -79,16 +79,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -97,8 +95,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -119,16 +115,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -137,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -166,6 +158,7 @@ cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 @@ -174,6 +167,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -190,7 +184,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr index 57ac24419..f7b481bbe 100644..100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr @@ -1,12 +1,10 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 -warn: Entering event queue @ 0. Starting simulation... -warn: Increasing stack size by one page. +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data -warn: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout new file mode 100755 index 000000000..3eda1fae9 --- /dev/null +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout @@ -0,0 +1,18 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:22:05 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:27:52 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py long/30.eon/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Eon, Version 1.1 +info: Increasing stack size by one page. +OO-style eon Time= 0.566667 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt index f6e3615e0..56640f3eb 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 948947 # Simulator instruction rate (inst/s) -host_mem_usage 204452 # Number of bytes of host memory used -host_seconds 420.11 # Real time elapsed on the host -host_tick_rate 1349967290 # Simulator tick rate (ticks/s) +host_inst_rate 1674592 # Simulator instruction rate (inst/s) +host_mem_usage 210700 # Number of bytes of host memory used +host_seconds 238.07 # Real time elapsed on the host +host_tick_rate 2383160323 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated -sim_seconds 0.567139 # Number of seconds simulated -sim_ticks 567138642000 # Number of ticks simulated +sim_seconds 0.567352 # Number of seconds simulated +sim_ticks 567351850000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 25398.947368 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22398.947368 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 24129000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 48286000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 21279000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 45436000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 73517416 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 89478000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 185584000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 3314 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 79536000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 175642000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 3314 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,46 +37,37 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26643.292683 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23643.292683 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 54847.560976 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency system.cpu.dcache.demand_hits 168270956 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 113607000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 233870000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses system.cpu.dcache.demand_misses 4264 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 100815000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 221078000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 4264 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26643.292683 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23643.292683 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 54847.560976 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 168270956 # number of overall hits -system.cpu.dcache.overall_miss_latency 113607000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 233870000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_misses 4264 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 100815000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 221078000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 4264 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3289.418113 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3288.899192 # Cycle average of tags in use system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 625 # number of writebacks @@ -93,13 +84,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 73520730 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.icache.ReadReq_accesses 398664666 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 25343.588347 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 22343.588347 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 50648.516199 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 398660993 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 93087000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 186032000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 82068000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 175013000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -111,46 +102,37 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 25343.588347 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 22343.588347 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 50648.516199 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency system.cpu.icache.demand_hits 398660993 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 93087000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 186032000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 82068000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 175013000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 25343.588347 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 22343.588347 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 398660993 # number of overall hits -system.cpu.icache.overall_miss_latency 93087000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 186032000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses system.cpu.icache.overall_misses 3673 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 82068000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 175013000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1769 # number of replacements system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1795.354000 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1795.124700 # Cycle average of tags in use system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -160,31 +142,31 @@ system.cpu.itb.acv 0 # IT system.cpu.itb.hits 398664666 # ITB hits system.cpu.itb.misses 173 # ITB misses system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 73646000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 166504000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 3202 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 35222000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 128080000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 3202 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 92874000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 209976000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 44418000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 112 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2576000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 5824000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1232000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4480000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) @@ -198,51 +180,42 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 585 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 166520000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 376480000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.925240 # miss rate for demand accesses system.cpu.l2cache.demand_misses 7240 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 79640000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 289600000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.925240 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 7240 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 585 # number of overall hits -system.cpu.l2cache.overall_miss_latency 166520000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 376480000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.925240 # miss rate for overall accesses system.cpu.l2cache.overall_misses 7240 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 79640000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 289600000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.925240 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 7240 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 15 # number of replacements system.cpu.l2cache.sampled_refs 4491 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3714.818787 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3714.176115 # Cycle average of tags in use system.cpu.l2cache.total_refs 540 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1134277284 # number of cpu cycles simulated +system.cpu.numCycles 1134703700 # number of cpu cycles simulated system.cpu.num_insts 398664609 # Number of instructions executed system.cpu.num_refs 174183455 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout deleted file mode 100644 index f9d497506..000000000 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout +++ /dev/null @@ -1,2 +0,0 @@ -Eon, Version 1.1 -OO-style eon Time= 0.566667 |