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author | Ali Saidi <saidi@eecs.umich.edu> | 2010-07-27 01:03:44 -0400 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2010-07-27 01:03:44 -0400 |
commit | 1b73376b0bb04f25b4a7ef80bcd6ad0739f5b926 (patch) | |
tree | 8deb8fa950c8c4045cb9492804ebfb6b5731499f /tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt | |
parent | 97d245278d4b4bee844c141c3b6f370e27f73a45 (diff) | |
download | gem5-1b73376b0bb04f25b4a7ef80bcd6ad0739f5b926.tar.xz |
ARM: Add regression tests
Diffstat (limited to 'tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt')
-rw-r--r-- | tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..624970b79 --- /dev/null +++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,36 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2179170 # Simulator instruction rate (inst/s) +host_mem_usage 205868 # Number of bytes of host memory used +host_seconds 158.12 # Real time elapsed on the host +host_tick_rate 1328711028 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 344575026 # Number of instructions simulated +sim_seconds 0.210099 # Number of seconds simulated +sim_ticks 210098857000 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 420197715 # number of cpu cycles simulated +system.cpu.num_insts 344575026 # Number of instructions executed +system.cpu.num_refs 177028576 # Number of memory references +system.cpu.workload.PROG:num_syscalls 191 # Number of system calls + +---------- End Simulation Statistics ---------- |